DSPIC30F6011A MICROCHIP [Microchip Technology], DSPIC30F6011A Datasheet - Page 155

• Manufacturer Part Number: DSPIC30F6011A
• Description: High-Performance Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

20.4
The dsPIC30F differentiates between various kinds of
Reset:
a)
b)
c)
d)
e)
f)
g)
h)
FIGURE 20-2:
© 2005 Microchip Technology Inc.
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
Watchdog Timer (WDT) Reset (during normal
operation)
Programmable Brown-out Reset (BOR)
RESET Instruction
Reset caused by trap lockup (TRAPR)
Reset caused by illegal opcode, or by using an
uninitialized W register as an Address Pointer
(IOPUWR)
MCLR
V
Illegal Opcode/
Uninitialized W Register
DD
Reset
Instruction
RESET
Trap Conflict
Brown-out
V
Sleep or Idle
Module
Detect
DD
WDT
Reset
RESET SYSTEM BLOCK DIAGRAM
Rise
dsPIC30F6011A/6012A/6013A/6014A
BOREN
Glitch Filter
Digital
POR
BOR
Preliminary
Different registers are affected in different ways by
various Reset conditions. Most registers are not
affected by a WDT wake-up, since this is viewed as the
resumption of normal operation. Status bits from the
RCON register are set or cleared differently in different
Reset situations, as indicated in Table 20-5. These bits
are used in software to determine the nature of the
Reset.
A block diagram of the on-chip Reset circuit is shown in
Figure 20-2.
A MCLR noise filter is provided in the MCLR Reset
path. The filter detects and ignores small pulses.
Internally generated Resets do not drive MCLR pin low.
S
R
Q
DS70143B-page 153
SYSRST