MC908GR16ACFA FREESCALE [Freescale Semiconductor, Inc], MC908GR16ACFA Datasheet
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MC68HC908GR16A Data Sheet M68HC08 Microcontrollers MC68HC908GR16A Rev. 1.0 03/2006 freescale.com ...
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MC68HC908GR16A Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, ...
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Revision History 4 MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
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List of Chapters Chapter 1 General Description ...
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List of Chapters 6 MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
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Table of Contents 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 6.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 14.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents Ordering Information and Mechanical Specifications 21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Chapter 1 General Description 1.1 Introduction The MC68HC908GR16A is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a ...
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General Description • Serial peripheral interface (SPI) module • Enhanced serial communications interface (ESCI) module • Fine adjust baud rate prescalers for precise control of baud rate • Arbiter module: – Measurement of received bit timings for baud rate recovery ...
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Features of the CPU08 Features of the CPU08 include: • Enhanced HC05 programming model • Extensive loop control functions • 16 addressing modes (eight more than the HC05) • 16-bit index register and stack pointer • Memory-to-memory data transfers ...
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General Description M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 64 BYTES USER FLASH — 15,872 BYTES USER RAM — 1024 BYTES MONITOR ROM — 350 BYTES FLASH PROGRAMMING ROUTINES ROM — 406 BYTES USER FLASH ...
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PTE0/TxD PTE1/RxD PTD0/SS PTD1/MISO PTD2/MOSI PTD3/SPSCK Figure 1-2. 32-Pin LQFP Pin Assignments RST 1 PTE0/TxD PTE1/RxD PTE2 PTE3 PTE4 PTE5 IRQ PTD0/SS PTD1/MISO PTD2/MOSI PTD3/SPSCK 12 Figure 1-3. 48-Pin LQFP Pin Assignments Freescale Semiconductor RST IRQ 4 ...
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General Description 1.5 Pin Functions Descriptions of the pin functions are provided here. 1.5.1 Power Supply Pins (V V and V are the power supply and ground pins. The MCU operates from a single power supply Fast signal ...
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CGM Power Supply Pins (V V and V are the power supply pins for the analog portion of the clock generator module (CGM). DDA SSA Decoupling of these pins should be as per the digital supply. See (CGM). 1.5.6 ...
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General Description 1.5.12 Port E I/O Pins (PTE5–PTE2 and PTE0/TxD) PTE5–PTE0 are general-purpose, bidirectional I/O port pins. PTE1 and PTE0 can also be programmed to be enhanced serial communications interface (ESCI) pins. PTE5–PTE2 are only available on the 48-pin LQFP ...
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Chapter 2 Memory 2.1 Introduction The CPU08 can address 64 Kbytes of memory space. The memory map, shown in • 15,872 bytes of user FLASH memory • 1024 bytes of random-access memory (RAM) • 406 bytes of FLASH programming routines ...
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Memory $0000 I/O REGISTERS ↓ 64 BYTES $003F $0040 RAM ↓ 1024 BYTES $043F $0440 UNIMPLEMENTED ↓ 192 BYTES $04FF $0500 RESERVED ↓ 128 BYTES $057F $0580 UNIMPLEMENTED ↓ 5760 BYTES $1BFF $1C00 FLASH PROGRAMMING ROUTINES ROM ↓ 406 BYTES ...
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Addr. Register Name Read: Port A Data Register $0000 (PTA) Write: See page 118. Reset: Read: Port B Data Register $0001 (PTB) Write: See page 120. Reset: Read: Port C Data Register $0002 (PTC) Write: See page 122. Reset: Read: ...
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Memory Addr. Register Name Read: Data Direction Register E $000C (DDRE) Write: See page 128. Reset: Read: Port A Input Pullup Enable $000D Register (PTAPUE) Write: See page 120. Reset: Read: Port C Input Pullup Enable $000E Register (PTCPUE) Write: ...
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Addr. Register Name Read: ESCI Data Register $0018 (SCDR) Write: See page 164. Reset: Read: ESCI Baud Rate Register $0019 (SCBR) Write: See page 165. Reset: Keyboard Status Read: and Control Register Write: $001A (INTKBSCR) Reset: See page 103. Read: ...
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Memory Addr. Register Name Read: Timer 1 Counter Modulo $0024 Register Low (T1MODL) Write: See page 227. Reset: Read: Timer 1 Channel 0 Status and $0025 Control Register (T1SC0) Write: See page 230. Reset: Read: Timer 1 Channel 0 $0026 ...
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Addr. Register Name Read: Timer 2 Channel 0 Status and $0030 Control Register (T2SC0) Write: See page 227. Reset: Read: Timer 2 Channel 0 $0031 Register High (T2CH0H) Write: See page 227. Reset: Read: Timer 2 Channel 0 $0032 Register ...
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Memory Addr. Register Name Read: ADC Status and Control $003C Register (ADSCR) Write: See page 51. Reset: Read: ADC Data High Register $003D (ADRH) Write: See page 53. Reset: Read: ADC Data Low Register $003E (ADRL) Write: See page 53. ...
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Addr. Register Name Read: FLASH Control Register $FE08 (FLCR) Write: See page 38. Reset: Read: Break Address Register High $FE09 (BRKH) Write: See page 235. Reset: Read: Break Address Register Low $FE0A (BRKL) Write: See page 235. Reset: Read: Break ...
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Memory Vector Priority Lowest Highest 36 . Table 2-1. Vector Addresses Vector Address $FFDC Timebase Vector (High) IF16 $FFDD Timebase Vector (Low) $FFDE ADC Conversion Complete Vector (High) IF15 $FFDF ADC Conversion Complete Vector (Low) $FFE0 Keyboard Vector (High) IF14 ...
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Random-Access Memory (RAM) Addresses $0040 through $043F are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space. For correct operation, the stack pointer ...
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Memory 2.6.2 FLASH Control Register The FLASH control register (FLCR) controls FLASH program and erase operations. Address: $FE08 Bit 7 Read: 0 Write: Reset Unimplemented Figure 2-3. FLASH Control Register (FLCR) HVEN — High-Voltage Enable Bit This read/write ...
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FLASH Page Erase Operation Use this step-by-step procedure to erase a page (64 bytes) of FLASH memory. A page consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80, or $XXC0. The 36-byte user interrupt vectors area also ...
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Memory Programming and erasing of FLASH locations cannot be performed by code being executed from FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. 2.6.5 FLASH Program/Read Operation Programming ...
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Do not exceed t cumulative high voltage programming time to the same row before next erase. t must satisfy this condition NVS Refer to 20.15 Memory The time between programming the FLASH address change (step 7 to step ...
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Memory Algorithm for programming a row (32 bytes) of FLASH memory Note: The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH address programmed to clearing PGM bit (step 7 to ...
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FLASH Block Protect Register The FLASH block protect register (FLBPR) is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. The value in this register determines ...
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Memory 2.6.8 Wait Mode Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly, but there will not be any memory activity since the CPU is inactive. ...
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Chapter 3 Analog-to-Digital Converter (ADC) 3.1 Introduction This section describes the 10-bit analog-to-digital converter (ADC). 3.2 Features Features of the ADC module include: • Eight channels with multiplexed input • Linear successive approximation with monotonicity • 10-bit resolution • Single ...
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Analog-to-Digital Converter (ADC) M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 64 BYTES USER FLASH — 15,872 BYTES USER RAM — 1024 BYTES MONITOR ROM — 350 BYTES FLASH PROGRAMMING ROUTINES ROM — 406 BYTES USER ...
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INTERNAL DATA BUS READ DDRBx WRITE DDRBx RESET WRITE PTBx READ PTBx CONVERSION COMPLETE INTERRUPT LOGIC AIEN COCO CGMXCLK BUS CLOCK 3.3.2 Voltage Conversion When the input voltage to the ADC equals V input voltage equals V the ADC converts ...
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Analog-to-Digital Converter (ADC) 3.3.3 Conversion Time Conversion starts after a write to the ADC status and control register (ADSCR). One conversion will take between 16 and 17 ADC clock cycles. The ADIVx and ADICLK bits should be set to provide ...
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ADC designs are required. No interlocking between ADRH and ADRL is present. Quantization error is affected when only the most significant eight bits are used as a result. See 8-BIT 10-BIT RESULT RESULT 003 ...
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Analog-to-Digital Converter (ADC) 3.6.1 Wait Mode The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU ...
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ADC Voltage Reference Low Pin (V The ADC analog portion uses V to the same voltage potential as V results. Any noise present on this pin will be reflected and possibly magnified in A/D conversion values. For maximum noise ...
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Analog-to-Digital Converter (ADC) AIEN — ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status/control register ...
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ADC Data Register High and Data Register Low 3.8.2.1 Left Justified Mode In left justified mode, the ADRH register holds the eight MSBs of the 10-bit result. The only difference from left justified mode is that the AD9 is ...
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Analog-to-Digital Converter (ADC) 3.8.2.3 Left Justified Signed Data Mode In left justified signed data mode, the ADRH register holds the eight MSBs of the 10-bit result. The only difference from left justified mode is that the AD9 is complemented. The ...
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ADC Clock Register The ADC clock register (ADCLK) selects the clock frequency for the ADC. Address: $003F Bit 7 Read: ADIV2 Write: Reset Figure 3-9. ADC Clock Register (ADCLK) ADIV2–ADIV0 — ADC Clock Prescaler Bits ADIV2–ADIV0 form ...
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Analog-to-Digital Converter (ADC) 56 MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
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Chapter 4 Clock Generator Module (CGM) 4.1 Introduction This section describes the clock generator module (CGM). The CGM generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal. The CGM also generates the base clock signal, ...
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Clock Generator Module (CGM) OSCILLATOR (OSC) OSC2 OSC1 SIMOSCEN (FROM SIM) OSCENINSTOP (FROM CONFIG) PHASE-LOCKED LOOP (PLL) V DDA PHASE DETECTOR LOCK DETECTOR LOCK MUL11–MUL0 CGMVDV FREQUENCY DIVIDER 58 CGMRCLK BCS CGMXFC V SSA VPR1–VPR0 VRS7–VRS0 VOLTAGE LOOP CONTROLLED FILTER ...
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Crystal Oscillator Circuit The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration ...
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Clock Generator Module (CGM) 4.3.4 Acquisition and Tracking Modes The PLL filter is manually or automatically configurable into one of two operating modes: • Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the VCO. ...
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The following conditions apply when in manual mode: • ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit must be clear. • Before entering tracking ...
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Clock Generator Module (CGM) 4. Select a VCO frequency multiplier Calculate and verify the adequacy of the VCO and bus frequencies f 6. Select the VCO’s power-of-two range multiplier E, according to Table 4-2. Power-of-Two Range Selectors 1. ...
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Table 4-3 provides numeric examples (register values are in hexadecimal notation): f (MHz) BUS 1.0 2.0 4.0 8.0 2.0 4.0 5.0 8.0 2.4576 4.9152 7.3728 2.0 4.0 6.0 8.0 4.3.7 Special Programming Exceptions The programming method described in exceptions. A ...
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Clock Generator Module (CGM) 4.3.9 CGM External Connections In its typical configuration, the CGM requires external components. Five of these are for the crystal oscillator and two or four are for the PLL. The crystal oscillator is normally connected in ...
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I/O Signals The following paragraphs describe the CGM I/O signals. 4.4.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier. 4.4.2 Crystal Amplifier Output Pin (OSC2) The OSC2 pin is the output ...
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Clock Generator Module (CGM) depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be unstable at start up. 4.4.9 CGM Base Clock Output (CGMOUT) CGMOUT is the clock output of the CGM. This ...
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PLL Control Register The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base clock selector bit, and the VCO power-of-two range selector bits. Address: $0036 Bit 7 Read: PLLIE Write: Reset: 0 ...
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Clock Generator Module (CGM) BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0), selecting CGMVCLK requires two writes to the PLL control register. (See 4.3.8 Base Clock Selector VPR1 and VPR0 — VCO ...
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LOCK — Lock Indicator Bit When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK, is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as ...
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Clock Generator Module (CGM) 4.5.4 PLL Multiplier Select Register Low The PLL multiplier select register low (PMSL) contains the programming information for the low byte of the modulo feedback divider. Address: $0038 Bit 7 Read: MUL7 Write: Reset: 0 Figure ...
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VRS7–VRS0 — VCO Range Select Bits These read/write bits control the hardware center-of-range linear multiplier L which, in conjunction with E (See 4.3.3 PLL Circuits, 4.3.6 Programming the hardware center-of-range frequency, f PCTL is set. (See 4.3.7 Special Programming register ...
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Clock Generator Module (CGM) 4.7.2 Stop Mode If the OSCENINSTOP bit in the CONFIG2 register is cleared (default), then the STOP instruction disables the CGM (oscillator and phase locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and CGMINT). ...
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The most critical parameter which affects the reaction times of the PLL is the reference frequency, f This frequency is the input to the phase detector and controls how often the PLL makes corrections. For stability, the corrections must be ...
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Clock Generator Module (CGM) Table 4-5. Example Filter Component Values f RCLK 1 MHz 2 MHz 3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz 8.2 nF 820 pF 4.7 nF 470 ...
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Chapter 5 Configuration Register (CONFIG) 5.1 Introduction This section describes the configuration registers, CONFIG1 and CONFIG2. The configuration registers enable or disable these options: • Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles) • COP timeout period ...
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Configuration Register (CONFIG) Address: $001F Bit 7 Read: COPRS LVISTOP Write: Reset: 0 Note: LVI5OR3 bit is only reset via POR (power-on reset). Figure 5-2. Configuration Register 1 (CONFIG1) TBMCLKSEL— Timebase Clock Select Bit TBMCLKSEL enables an extra divide-by-128 prescaler ...
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LVIPWRD — LVI Power Disable Bit LVIPWRD disables the LVI module. See 1 = LVI module power disabled 0 = LVI module power enabled LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit LVI5OR3 selects the voltage operating mode of ...
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Configuration Register (CONFIG) 78 MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
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Chapter 6 Computer Operating Properly (COP) Module 6.1 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset ...
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Computer Operating Properly (COP) Module The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176 CGMXCLK cycles, depending ...
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Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler. 6.3.7 COPD (COP Disable) The COPD signal reflects the state of the COP disable ...
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Computer Operating Properly (COP) Module 6.7.2 Stop Mode Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout ...
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Chapter 7 Central Processor Unit (CPU) 7.1 Introduction The M68HC08 CPU (central processor unit enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction ...
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Central Processor Unit (CPU 7.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Bit 7 Read: Write: Reset: 7.3.2 Index Register The ...
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Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least ...
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Central Processor Unit (CPU) 7.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following ...
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Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00 Zero result 0 = Non-zero result C — Carry/Borrow Flag The CPU sets the ...
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Central Processor Unit (CPU) 7.7 Instruction Set Summary Table 7-1 provides a summary of the M68HC08 instruction set. Table 7-1. Instruction Set Summary (Sheet Source Operation Form ADC #opr ADC opr ADC opr ADC opr,X Add with ...
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Table 7-1. Instruction Set Summary (Sheet Source Operation Form Branch if Higher or Same BHS rel (Same as BCC) BIH rel Branch if IRQ Pin High BIL rel Branch if IRQ Pin Low BIT #opr BIT opr ...
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Central Processor Unit (CPU) Table 7-1. Instruction Set Summary (Sheet Source Operation Form CLR opr CLRA CLRX CLRH Clear CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X Compare A with M ...
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Table 7-1. Instruction Set Summary (Sheet Source Operation Form JMP opr JMP opr JMP opr,X Jump JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X Jump to Subroutine JSR opr,X JSR ,X LDA #opr LDA opr ...
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Central Processor Unit (CPU) Table 7-1. Instruction Set Summary (Sheet Source Operation Form PULA Pull A from Stack PULH Pull H from Stack PULX Pull X from Stack ROL opr ROLA ROLX Rotate Left through Carry ROL ...
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Table 7-1. Instruction Set Summary (Sheet Source Operation Form SWI Software Interrupt TAP Transfer A to CCR TAX Transfer TPA Transfer CCR to A TST opr TSTA TSTX Test for Negative or Zero TST ...
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Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...
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Chapter 8 External Interrupt (IRQ) 8.1 Introduction The IRQ (external interrupt) module provides a maskable interrupt input. 8.2 Features Features of the IRQ module include: • A dedicated external interrupt pin (IRQ) • IRQ interrupt control bits • Hysteresis buffer ...
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External Interrupt (IRQ) RESET ACK VECTOR FETCH DECODER V DD INTERNAL PULLUP DEVICE IRQ When an interrupt pin is both falling-edge and low-level triggered (MODE = 1), the interrupt remains set until both of these events occur: • Vector fetch ...
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IRQ Pin A falling edge on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is ...
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External Interrupt (IRQ) 8.6 IRQ Status and Control Register The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The INTSCR: • Shows the state of the IRQ flag • Clears the IRQ latch • ...
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Chapter 9 Keyboard Interrupt Module (KBI) 9.1 Introduction The keyboard interrupt module (KBI) provides eight independently maskable external interrupts which are accessible via PTA0–PTA7. When a port pin is enabled for keyboard interrupt function, an internal pullup device is also ...
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Keyboard Interrupt Module (KBI) M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 64 BYTES USER FLASH — 15,872 BYTES USER RAM — 1024 BYTES MONITOR ROM — 350 BYTES FLASH PROGRAMMING ROUTINES ROM — 406 BYTES ...
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INTERNAL BUS VECTOR FETCH DECODER RESET KBD0 . TO PULLUP ENABLE . KB0IE . KBD7 TO PULLUP ENABLE KB7IE Figure 9-2. Keyboard Module Block Diagram Addr. Register Name Keyboard Status Read: and Control Register Write: $001A (INTKBSCR) Reset: See page ...
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Keyboard Interrupt Module (KBI) The vector fetch or software clear and the return of all enabled keyboard interrupt pins to a high level may occur in any order. If the MODEK bit is clear, the keyboard interrupt pin is falling-edge-sensitive ...
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Stop Mode The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. 9.6 Keyboard Module During Break Interrupts ...
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Keyboard Interrupt Module (KBI) IMASKK — Keyboard Interrupt Mask Bit Writing this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. Reset clears the IMASKK bit Keyboard interrupt requests masked ...
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Chapter 10 Low-Power Modes 10.1 Introduction The microcontroller (MCU) may enter two low-power modes: wait mode and stop mode. They are common to all HC08 MCUs and are entered through instruction execution. This section describes how each module acts in ...
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Low-Power Modes 10.3 Break Module (BRK) 10.3.1 Wait Mode The break (BRK) module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if the SBSW bit in the ...
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Computer Operating Properly Module (COP) 10.6.1 Wait Mode The COP remains active during wait mode. If COP is enabled, a reset will occur at COP timeout. 10.6.2 Stop Mode Stop mode turns off the COPCLK input to the COP ...
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Low-Power Modes 10.9 Low-Voltage Inhibit Module (LVI) 10.9.1 Wait Mode If enabled, the low-voltage inhibit (LVI) module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of ...
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Timer Interface Module (TIM1 and TIM2) 10.12.1 Wait Mode The timer interface modules (TIM) remain active in wait mode. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are ...
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Low-Power Modes • Timebase module (TBM) interrupt — A TBM interrupt loads the program counter with the contents of locations $FFDC and $FFDD when the timebase counter has rolled over. This allows the TBM to generate a periodic wakeup from ...
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Chapter 11 Low-Voltage Inhibit (LVI) 11.1 Introduction This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the V and can force a reset when the V 11.2 Features Features of the LVI module include: • Programmable ...
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Low-Voltage Inhibit (LVI) LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration register (CONFIG1). See Figure 5-2. Configuration Register 1 (CONFIG1) reset occurs, the MCU remains in reset until V to exit reset. See 15.3.2.5 Low-Voltage Inhibit (LVI) Reset and ...
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Voltage Hysteresis Protection Once the LVI has triggered (by having V V rises above the rising trip point voltage continually entering and exiting reset the hysteresis voltage, V TRIPF 11.3.4 LVI Trip Selection ...
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Low-Voltage Inhibit (LVI) 11.6.1 Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 11.6.2 Stop Mode If ...
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Chapter 12 Input/Output (I/O) Ports 12.1 Introduction Bidirectional input-output (I/O) pins form five parallel ports. All I/O pins are programmable as inputs or outputs. All individual bits within port A, port C, and port D are software configurable with pullup ...
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Input/Output (I/O) Ports Addr. Register Name Read: Data Direction Register B $0005 (DDRB) Write: See page 121. Reset: Read: Data Direction Register C $0006 (DDRC) Write: See page 122. Reset: Read: Data Direction Register D $0007 (DDRD) Write: See page ...
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Table 12-1. Port Control Register Bits Summary Port Bit ...
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Input/Output (I/O) Ports 12.2 Port A Port 8-bit special-function port that shares all eight of its pins with the keyboard interrupt (KBI) module. Port A also has software configurable pullup devices if configured as an input port. ...
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Figure 12-4 shows the port A I/O logic. READ DDRA ($0004) WRITE DDRA ($0004) WRITE PTA ($0000) READ PTA ($0000) When bit DDRAx reading address $0000 reads the PTAx data latch. When bit DDRAx ...
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Input/Output (I/O) Ports 12.2.3 Port A Input Pullup Enable Register The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each of the eight port A pins. Each bit is individually configurable and requires that ...
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Data Direction Register B Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing DDRB bit enables the output buffer for the corresponding port B pin; a ...
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Input/Output (I/O) Ports 12.4 Port C Port 7-bit, general-purpose bidirectional I/O port. Port C also has software configurable pullup devices if configured as an input port. 12.4.1 Port C Data Register The port C data register (PTC) ...
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Figure 12-11 shows the port C I/O logic. READ DDRC ($0006) WRITE DDRC ($0006) WRITE PTC ($0002) READ PTC ($0002) When bit DDRCx reading address $0002 reads the PTCx data latch. When bit DDRCx ...
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Input/Output (I/O) Ports 12.4.3 Port C Input Pullup Enable Register The port C input pullup enable register (PTCPUE) contains a software configurable pullup device for each of the seven port C pins. Each bit is individually configurable and requires that ...
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T1CH1 and T1CH0 — Timer 1 Channel I/O Bits The PTD7/T1CH1–PTD6/T1CH0 pins are the TIM1 input capture/output compare pins. The edge/level select bits, ELSxB and ELSxA, determine whether the PTD7/T1CH1–PTD6/T1CH0 pins are timer channel I/O pins or general-purpose I/O pins. ...
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Input/Output (I/O) Ports Figure 12-15 shows the port D I/O logic. READ DDRD ($0007) WRITE DDRD ($0007) WRITE PTD ($0003) READ PTD ($0003) When bit DDRDx reading address $0003 reads the PTDx data latch. When bit DDRDx ...
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Port D Input Pullup Enable Register The port D input pullup enable register (PTDPUE) contains a software configurable pullup device for each of the eight port D pins. Each bit is individually configurable and requires that the data direction ...
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Input/Output (I/O) Ports RxD — SCI Receive Data Input The PTE1/RxD pin is the receive data input for the ESCI module. When the enable SCI bit, ENSCI, is clear, the ESCI module is disabled, and the PTE1/RxD pin is available ...
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When bit DDREx reading address $0008 reads the PTEx data latch. When bit DDREx reading address $0008 reads the voltage level on the pin. The data latch can always be written, regardless of the ...
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Input/Output (I/O) Ports 130 MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
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Chapter 13 Resets and Interrupts 13.1 Introduction Resets and interrupts are responses to exceptional events during program execution. A reset re-initializes the microcontroller (MCU) to its startup condition. An interrupt vectors the program counter to a service routine. 13.2 Resets ...
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Resets and Interrupts A power-on reset: • Holds the clocks to the central processor unit (CPU) and modules inactive for an oscillator stabilization delay of 4096 CGMXCLK cycles • Drives the RST pin low during the oscillator stabilization delay • ...
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If the stop enable bit, STOP, in the CONFIG1 register the STOP instruction causes an illegal opcode reset. 13.2.3.5 Illegal Address Reset An illegal address reset is an internal reset caused by opcode fetch from an unmapped ...
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Resets and Interrupts MODRST — Monitor Mode Entry Module Reset Bit 1 = Last reset caused by forced monitor mode entry POR or read of SRSR since any reset LVI — Low-Voltage Inhibit Reset Bit 1 = Last ...
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Figure 13- interrupt is pending upon exit from the interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed. INT1 INT2 Figure 13-4 The LDA opcode is prefetched by both the ...
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Resets and Interrupts FROM RESET INTERRUPT YES I BIT SET? I BIT SET? INTERRUPT INTERRUPT INTERRUPTS FETCH NEXT INSTRUCTION INSTRUCTION INSTRUCTION 136 YES BREAK ? NO NO YES IRQ ? NO YES CGM ? NO OTHER YES ? NO STACK ...
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Source Reset SWI instruction IRQ pin CGM change in lock TIM1 channel 0 TIM1 channel 1 TIM1 overflow TIM2 channel 0 TIM2 channel 1 TIM2 overflow SPI receiver full SPI overflow SPI mode fault SPI transmitter empty SCI receiver overrun ...
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Resets and Interrupts 13.3.2.3 IRQ Pin the IRQ pin latches an external interrupt request. 13.3.2.4 Clock Generator (CGM) The CGM can generate a CPU interrupt request every time the phase-locked loop circuit (PLL) enters or leaves the ...
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Overflow bit (OVRF) — The OVRF bit is set if software does not read the byte in the receive data register before the next full byte enters the shift register. The error interrupt enable bit, ERRIE, enables OVRF CPU ...
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Resets and Interrupts Interrupts must be acknowledged by writing the TACK bit. 13.3.3 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. Table 13-2 summarizes the interrupt sources and the interrupt status ...
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Interrupt Status Register 2 Address: $FE05 Bit 7 Read: IF14 Write: R Reset Figure 13-7. Interrupt Status Register 2 (INT2) IF14–IF7 — Interrupt Flags 14–7 These flags indicate the presence of interrupt requests from the sources shown ...
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Resets and Interrupts 142 MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
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Chapter 14 Enhanced Serial Communications Interface (ESCI) Module 14.1 Introduction The enhanced serial communications interface (ESCI) module allows asynchronous communications with peripheral devices and other microcontroller units (MCU). 14.2 Features Features include: • Full-duplex operation • Standard mark/space non-return-to-zero (NRZ) ...
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Enhanced Serial Communications Interface (ESCI) Module M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 64 BYTES USER FLASH — 15,872 BYTES USER RAM — 1024 BYTES MONITOR ROM — 350 BYTES FLASH PROGRAMMING ROUTINES ROM — ...
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Functional Description Figure 14-2 shows the structure of the ESCI module. The ESCI allows full-duplex, asynchronous, NRZ serial communication between the MCU and remote devices, including other MCUs. The transmitter and receiver of the ESCI operate independently, although they ...
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Enhanced Serial Communications Interface (ESCI) Module The baud rate clock source for the ESCI can be selected via the configuration bit, ESCIBDSRC, of the CONFIG2 register ($001E). For reference, a summary of the ESCI module input/output registers is provided in ...
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Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in START BIT BIT 0 BIT 1 START BIT BIT 0 BIT 1 14.4.2 Transmitter Figure 14-5 shows the structure of the SCI transmitter and the registers ...
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Enhanced Serial Communications Interface (ESCI) Module 14.4.2.1 Character Length The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in ESCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in ...
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Clears the R8 bit in SCC3 • Sets the break flag bit (BKF) in SCS2 • May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits 14.4.2.4 Idle Characters For TXINV ...
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Enhanced Serial Communications Interface (ESCI) Module LINR SCP1 SCP0 PRE- ÷ 4 SCALER BKF PDS2 RPF PDS1 CGMXCLK OR PDS0 BUS CLOCK PSSB4 WAKE PSSB3 ILTY PSSB2 PSSB1 PEN PSSB0 PTY CPU INTERRUPT REQUEST ERROR CPU INTERRUPT REQUEST Figure 14-6. ...
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Character Reception During an ESCI reception, the receive shift register shifts characters in from the RxD pin. The ESCI data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register. After a complete ...
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Enhanced Serial Communications Interface (ESCI) Module If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. To determine the value of a data bit and to detect noise, recovery ...
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In most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge within ...
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Enhanced Serial Communications Interface (ESCI) Module RECEIVER RT CLOCK For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times × cycles + 10 RT cycles = 154 RT cycles. With the misaligned ...
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With the WAKE bit clear, setting the RWU bit after the RxD pin has been idle will cause the receiver to wake up. 14.4.3.7 Receiver Interrupts These sources can generate CPU interrupt requests from the ESCI receiver: • ESCI receiver ...
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Enhanced Serial Communications Interface (ESCI) Module 14.6 ESCI During Break Module Interrupts The BCFE bit in the break flag control register (SBFCR) enables software to clear status bits during the break state. See Chapter 19 Development To allow software to ...
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ESCI Control Register 1 ESCI control register 1 (SCC1): • Enables loop mode operation • Enables the ESCI • Controls output polarity • Controls character length • Controls ESCI wakeup method • Controls idle character detection • Enables parity ...
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Enhanced Serial Communications Interface (ESCI) Module Control Bits M PEN:PTY WAKE — Wakeup Condition Bit This read/write bit determines which condition wakes ...
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Enables the transmitter • Enables the receiver • Enables ESCI wakeup • Transmits ESCI break characters Address: $0014 Bit 7 Read: SCTIE Write: Reset: 0 Figure 14-11. ESCI Control Register 2 (SCC2) SCTIE — ESCI Transmit Interrupt Enable Bit ...
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Enhanced Serial Communications Interface (ESCI) Module RE — Receiver Enable Bit Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not affect receiver interrupt flag bits. Reset clears the RE bit ...
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When the ESCI is receiving 8-bit characters copy of the eighth bit (bit 7). Reset has no effect on the R8 bit. T8 — Transmitted Bit 8 When the ESCI is transmitting 9-bit characters the ...
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Enhanced Serial Communications Interface (ESCI) Module SCTE — ESCI Transmitter Empty Bit This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register. SCTE can generate an ESCI transmitter CPU interrupt request. When the ...
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In applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after reading ...
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Enhanced Serial Communications Interface (ESCI) Module 14.8.5 ESCI Status Register 2 ESCI status register 2 (SCS2) contains flags to signal these conditions: • Break character detected • Incoming data Address: $0017 Bit 7 Read: 0 Write: Reset: 0 Figure 14-15. ...
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ESCI Baud Rate Register The ESCI baud rate register (SCBR) together with the ESCI prescaler register selects the baud rate for both the receiver and the transmitter. There are two prescalers available to adjust the baud rate. One in ...
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Enhanced Serial Communications Interface (ESCI) Module node to differentiate between a 0x00 character of 10.35 bits and a break character of 11.05 bits. The break symbol length must be verified in software in any case, but the LINR bit serves ...
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PDS2–PDS0 — Prescaler Divisor Select Bits These read/write bits select the prescaler divisor as shown in The setting of ‘000’ will bypass not only this prescaler but also the prescaler divisor fine adjust (PDFA not recommended to bypass ...
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Enhanced Serial Communications Interface (ESCI) Module Table 14-11. ESCI Prescaler Divisor Fine Adjust (Continued) PSSB[4:3:2:1: ...
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Table 14-12. ESCI Baud Rate Selection Examples PS[2:1:0] PSSB[4:3:2:1: ...
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Enhanced Serial Communications Interface (ESCI) Module 14.9 ESCI Arbiter The ESCI module comprises an arbiter module designed to support software for communication tasks as bus arbitration, baud rate recovery and break time detection. The arbiter module consists of an 9-bit ...
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AROVFL— Arbiter Counter Overflow Bit This read-only bit indicates an arbiter counter overflow. Clear AROVFL by writing any value to SCIACTL. Writing 0s to AM1 and AM0 resets the counter keeps it in this idle state. Reset clears AROVFL. 1 ...
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Enhanced Serial Communications Interface (ESCI) Module RXD Figure 14-21. Bit Time Measurement with ACLK = 0 RXD Figure 14-22. Bit Time Measurement with ACLK = 1, Scenario A RXD Figure 14-23. Bit Time Measurement with ACLK = 1, Scenario B ...
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Chapter 15 System Integration Module (SIM) 15.1 Introduction This section describes the system integration module (SIM). Together with the central processor unit (CPU), the SIM controls all microcontroller unit (MCU) activities. A block diagram of the SIM is shown in ...
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System Integration Module (SIM) The SIM is responsible for: • Bus clock generation and control for CPU and peripherals: – Stop/wait/reset/break entry and recovery – Internal clock control • Master reset control, including power-on reset (POR) and computer operating properly ...
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SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in originates from either an ...
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System Integration Module (SIM) 15.3 Reset and System Initialization The MCU has these reset sources: • Power-on reset module (POR) • External reset pin (RST) • Computer operating properly module (COP) • Low-voltage inhibit module (LVI) • Illegal opcode • ...
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IRST RST CGMXCLK IAB Reset Recovery Type POR/LVI All others 15.3.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST) ...
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System Integration Module (SIM) OSC1 PORRST 4096 CYCLES CGMXCLK CGMOUT RST IRST IAB 15.3.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal ...
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SIM counter counts out 4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively pulls down the RST pin for all ...
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System Integration Module (SIM) 15.5.1 Interrupts At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the ...
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Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, ...
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System Integration Module (SIM) 15.5.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware ...
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Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. Table 15-3 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging. Priority ...
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System Integration Module (SIM) Interrupt Status Register 2 Address: $FE05 Bit 7 Read: I14 Write: R Reset Figure 15-13. Interrupt Status Register 2 (INT2) I14–I7 — Interrupt Flags 14–7 These flags indicate the presence of interrupt requests from ...
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Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Setting the BCFE bit enables ...
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System Integration Module (SIM) IAB IDB $A6 EXITSTOPWAIT Note: EXITSTOPWAIT = RST pin or CPU interrupt Figure 15-16. Wait Recovery from Interrupt IAB $6E0B IDB $A6 $A6 RST CGMXCLK Figure 15-17. Wait Recovery from Internal Reset 15.6.2 Stop Mode In ...
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CPUSTOP IAB STOP ADDR IDB R/W Note: Previous data can be operand data or the STOP opcode, depending on the last instruction. CGMXCLK INT/BREAK IAB STOP +1 Figure 15-19. Stop Mode Recovery from Interrupt 15.7 SIM Registers The SIM has ...
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System Integration Module (SIM) SBSW — SIM Break Stop/Wait SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it Wait mode was exited ...
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SIM Break Flag Control Register The SIM break flag control register (SBFCR) contains a bit that enables software to clear status bits while the MCU break state. Address: $FE03 Bit 7 Read: BCFE Write: Reset: 0 ...
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System Integration Module (SIM) 190 MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
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Chapter 16 Serial Peripheral Interface (SPI) Module 16.1 Introduction This section describes the serial peripheral interface (SPI) module, which allows full-duplex, synchronous, serial communications with peripheral devices. The text that follows describes the SPI. The SPI I/O pin names are ...
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Serial Peripheral Interface (SPI) Module M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 64 BYTES USER FLASH — 15,872 BYTES USER RAM — 1024 BYTES MONITOR ROM — 350 BYTES FLASH PROGRAMMING ROUTINES ROM — 406 ...
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BUSCLK ÷ 2 ÷ 8 CLOCK DIVIDER ÷ 32 ÷ 128 CLOCK SPMSTR SPE SELECT SPR1 TRANSMITTER CPU INTERRUPT REQUEST RECEIVER/ERROR CPU INTERRUPT REQUEST Addr. Register Name Read: SPI Control Register $0010 (SPCR) Write: See page 207. Reset: Read: SPI ...
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Serial Peripheral Interface (SPI) Module 16.3.1 Master Mode The SPI operates in master mode when the SPI master bit, SPMSTR, is set multi-SPI system, configure the SPI modules as master or slave before enabling them. Enable the master ...
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The maximum frequency of the SPSCK for an SPI configured as a slave is the bus clock speed (which is twice as fast as the fastest master SPSCK clock that can be generated). The frequency of the SPSCK for an ...
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Serial Peripheral Interface (SPI) Module input (SS) is low, so that only the selected slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master ...
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I/O not affecting the SPI. (See 16.6.2 Mode Fault Error.) When CPHA = 1, the master begins driving its MOSI pin on the first SPSCK edge. Therefore, ...
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Serial Peripheral Interface (SPI) Module WRITE TO SPDR BUS CLOCK MOSI SPSCK CPHA = 1 SPSCK CPHA = 0 SPSCK CYCLE NUMBER WRITE TO SPDR BUS CLOCK WRITE TO SPDR BUS CLOCK WRITE TO SPDR BUS CLOCK WRITE TO SPDR ...
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Queuing Transmission Data The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI ...
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Serial Peripheral Interface (SPI) Module 16.6 Error Conditions The following flags signal SPI error conditions: • Overflow (OVRF) — Failing to read the SPI data register before the next full byte enters the shift register sets the OVRF bit. The ...