MCF5212 FREESCALE [Freescale Semiconductor, Inc], MCF5212 Datasheet - Page 26

• Manufacturer Part Number: MCF5212
• Description: Microcontroller Family Hardware Specification
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

MCF5213 Family Configurations
26
Processor Status Clock
All Processor Status
Development Serial
Development Serial
Development Serial
Test Data Output
Processor Status
Test Data Input
Signal Name
Debug Data
Breakpoint
Outputs
Outputs
Output
Clock
Input
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
Abbreviation
DDATA[3:0]
PSTCLK
PST[3:0]
ALLPST
DSCLK
BKPT
TDO
DSO
TDI
DSI
Table 16. Debug Support Signals (continued)
Serial input for test instructions and data. TDI is sampled on the rising
edge of TCLK.
Serial output for test instructions and data. TDO is tri-stateable and is
actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCLK.
Development Serial Clock-Internally synchronized input. (The logic
level on DSCLK is validated if it has the same value on two
consecutive rising bus clock edges.) Clocks the serial communication
port to the debug module during packet transfers. Maximum frequency
is PSTCLK/5. At the synchronized rising edge of DSCLK, the data
input on DSI is sampled and DSO changes state.
Breakpoint - Input used to request a manual breakpoint. Assertion of
BKPT puts the processor into a halted state after the current
instruction completes. Halt status is reflected on processor
status/debug data signals (PST[3:0]PSTDDATA[7:0]) as the value 0xF.
If CSR[BKD] is set (disabling normal BKPT functionality), asserting
BKPT generates a debug interrupt exception in the processor.
Development Serial Input -Internally synchronized input that provides
data input for the serial communication port to the debug module,
once the DSCLK has been seen as high (logic 1).
Development Serial Output -Provides serial output communication for
debug module responses. DSO is registered internally. The output is
delayed from the validation of DSCLK high.
Display captured processor data and breakpoint status. The CLKOUT
signal can be used by the development system to know when to
sample DDATA[3:0].
Processor Status Clock - Delayed version of the processor clock. Its
rising edge appears in the center of valid PST and DDATA output.
PSTCLK indicates when the development system should sample PST
and DDATA values.
If real-time trace is not used, setting CSR[PCD] keeps PSTCLK, and
PST and DDATA outputs from toggling without disabling triggers.
Non-quiescent operation can be reenabled by clearing CSR[PCD],
although the external development systems must resynchronize with
the PST and DDATA outputs.
PSTCLK starts clocking only when the first non-zero PST value (0xC,
0xD, or 0xF) occurs during system reset exception processing.
Indicate core status. Debug mode timing is synchronous with the
processor clock; status is unrelated to the current bus transfer. The
CLKOUT signal can be used by the development system to know
when to sample PST[3:0].
Logical “AND” of PST[3.0]
Preliminary
Function
Freescale Semiconductor
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