MCF5485 FREESCALE [Freescale Semiconductor, Inc], MCF5485 Datasheet - Page 19

• Manufacturer Part Number: MCF5485
• Description: Integrated Microprocessor Electrical Characteristics
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale Semiconductor
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DDR memories typically have a minimum speed specification of 83 MHz. Check with memory component specifications to
verify.
The frequency of operation is 2x or 4x the CLKIN frequency of operation. The MCF548X supports a single external
reference clock (CLKIN). This signal defines the frequency of operation for FlexBus and PCI, but SDRAM clock operates at
the same frequency as the internal bus clock. Please see the reset configuration signals description in the “Signal
Descriptions” chapter within the MCF548x Reference Manual.
SDCLK is one memory clock in (ns).
Pulse width high plus pulse width low cannot exceed max clock period.
Pulse width high plus pulse width low cannot exceed max clock period.
Command output valid should be 1/2 the memory bus clock (SDCLK) plus some minor adjustments for process,
temperature, and voltage variations.
This specification relates to the required input setup time of today’s DDR memories. SDDATA[31:24] is relative to SDDQS3,
SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0.
The first data beat is valid before the first rising edge of SDDQS and after the SDDQS write preamble. The remaining data
beats is valid for each subsequent SDDQS edge.
This specification relates to the required hold time of today’s DDR memories. SDDATA[31:24] is relative to SDDQS3,
SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0.
Data input skew is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the last data
line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing
or other factors).
Data input hold is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the first data
line becomes invalid.
DQS input read preamble width (t
DQS input read postamble width (t
DQS output write preamble width (t
DQS output write postamble width (t
MCF5485 Integrated Microprocessor Electrical Characteristics, Rev. 3
Table 13. DDR Timing Specifications (continued)
Characteristic
RPRE
RPST
WPRE
WPST
)
)
)
)
0.25
Min
0.9
0.4
0.4
SDR SDRAM AC Timing Characteristics
Max
1.1
0.6
0.6
—
SDCLK
SDCLK
SDCLK
SDCLK
Unit
Notes
—
—
—
—
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