SCF5249VM140 FREESCALE [Freescale Semiconductor, Inc], SCF5249VM140 Datasheet - Page 17

• Manufacturer Part Number: SCF5249VM140
• Description: Integrated ColdFire Microprocessor
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

8.2
Many pins have a GPIO as first or second function. If GPIO is second function, following rules apply:
8.3
These signals provide the external bus interface to the SCF5249.
8.3.1
8.3.2
This signal indicates during any bus cycle whether a read or write is in progress. A low is write cycle and
a high is a read cycle.
8.3.3
The OE signal is intended to be connected to the output enable of asynchronous memories connected to
chip selects. During bus read cycles, the ColdFire processor will drive OE low.
8.3.4
The data bus (D[31:16]) is bi-directional and non-multiplexed. Data is registered by the SCF5249 on the
rising clock edge. The port width for each chip-select and DRAM bank are programmable. The data bus
uses a default configuration if none of the chip-selects or DRAM bank match the address decode. All 16
bits of the data bus are driven during writes, regardless of port width or operand size.
8.3.5
The TA/GPIO20 pin is the transfer acknowledge signal.
Freescale Semiconductor
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General purpose input is always active, regardless of state of pin.
General purpose output or primary output is determined by value written to GPIO function select
register.
Power-on reset function is not GPIO.
The address bus provides the address of the byte or most significant byte of the word or longword
being transferred.The address lines also serve as the DRAM address pins, providing multiplexed
row and column address signals.
Bits 23 down to 1 and 25 of the address are available. A25 is intended to be used with 256 Mbit
DRAM’s. Signals are named:
A[23:1]
A[25]/GPO8
GPIO
SCF5249 Bus Signals
Address Bus
Read-Write Control
Output Enable
Data Bus
Transfer Acknowledge
SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3
Signal Descriptions
17