SCF5249VM140 FREESCALE [Freescale Semiconductor, Inc], SCF5249VM140 Datasheet - Page 7

• Manufacturer Part Number: SCF5249VM140
• Description: Integrated ColdFire Microprocessor
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

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5.1
The ColdFire processor Version 2 core consists of two independent, decoupled pipeline structures to
maximize performance while minimizing core size.The instruction fetch pipeline (IFP) is a two-stage
pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage
operand execution pipeline (OEP), which decodes the instruction, fetches the required operands, and then
executes the required function. Because the IFP and OEP pipelines are decoupled by an instruction buffer
that serves as a FIFO queue, the IFP can prefetch instructions in advance of their actual use by the OEP,
which minimizes time stalled waiting for instructions. The OEP is implemented in a two-stage pipeline
featuring a traditional RISC data path with a dual-read-ported register file feeding an arithmetic/logic unit
(ALU).
5.2
The SCF5249 provides four fully programmable DMA channels for quick data transfer. Single and dual
address mode is supported with the ability to program bursting and cycle stealing. Data transfer is
selectable as 8, 16, 32, or 128-bits. Packing and unpacking is supported.
Freescale Semiconductor
SCF5249 Functional Overview
ColdFire V2 Core
DMA Controller
SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3
160 MAPBGA
Ball Number
G12
K11
F13
F12
E3
G4
H3
K3
N8
P9
E8
B8
E7
A7
L4
L8
Table 2. 160 MAPBGA Ball Assignments
RSTO/sdata2_bs2
SDRAM_CS2
sdata0_sdio1
cmd_sdio2
QSPI_CS1
QSPI_CS3
BUFENb2
Function
EbuOut2
sclk3
SWE
SRE
lrck3
subr
A25
sfsy
rck
gpio 53
gpio 52
gpio 51
gpio 45
gpio 49
gpio34
gpio54
gpio24
gpio22
gpo 37
gpio17
gpio11
gpio12
GPIO
gpio7
gpo8
SCF5249 Functional Overview
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