MC9S12DJ256 MOTOROLA [Motorola, Inc], MC9S12DJ256 Datasheet - Page 22
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MC9S12DJ256
Manufacturer Part Number
MC9S12DJ256
Description
MC9S12DT256 Device User Guide V03.03
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC9S12DJ256.pdf
(130 pages)
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MC9S12DT256 Device User Guide — V03.03
20
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– Programmable rising or falling edge trigger
Memory
– 256K Flash EEPROM
– 4K byte EEPROM
– 12K byte RAM
– 10-bit resolution
– External conversion trigger capability
Three 1M bit per second, CAN 2.0 A, B software compatible modules
– Five receive and three transmit buffers
– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
– Four separate interrupt channels for Rx, Tx, error and wake-up
– Low-pass filter wake-up function
– Loop-back for self test operation
Enhanced Capture Timer
– 16-bit main counter with 7-bit prescaler
– 8 programmable input capture or output compare channels
– Four 8-bit or two 16-bit pulse accumulators
8 PWM channels
– Programmable period and duty cycle
– 8-bit 8-channel or 16-bit 4-channel
– Separate control for each pulse width and duty cycle
– Center-aligned or left-aligned outputs
– Programmable clock select logic with a wide range of frequencies
– Fast emergency shutdown input
– Usable as interrupt inputs
Serial interfaces
– Two asynchronous Serial Communications Interfaces (SCI)
– Three Synchronous Serial Peripheral Interface (SPI)
Byte Data Link Controller (BDLC)
– SAE J1850 Class B Data Communications Network Interface Compatible and ISO Compatible
Inter-IC Bus (IIC)
Two 8-channel Analog-to-Digital Converters
for Low-Speed (<125 Kbps) Serial Data Communications in Automotive Applications