MC9RS08KA1 FREESCALE [Freescale Semiconductor, Inc], MC9RS08KA1 Datasheet
MC9RS08KA1
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MC9RS08KA1 Summary of contents
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... MC9RS08KA2 MC9RS08KA1 Data Sheet RS08 Microcontrollers MC9RS08KA2 Rev. 4 12/2008 freescale.com ...
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... Index addressing via D[X] and X register • Direct page access to the entire memory map through paging window Memory • On-chip Flash EEPROM — MC9RS08KA2: 2048 bytes — MC9RS08KA1: 1024 bytes • 63 bytes on-chip RAM Power-Saving Modes • Wait and stop • Wakeup from power-saving modes using ...
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MC9RS08KA2 Series Data Sheet, Rev. 4 Freescale Semiconductor ...
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... MC9RS08KA2 Series Data Sheet Covers: MC9RS08KA2 MC9RS08KA1 MC9RS08KA2 Rev. 4 12/2008 ...
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... Date 1.0 04/2006 Initial public release version 2 12/2006 Added MC9RS08KA1 Corrected Instruction Set Summary LDX ,X row operand to read 0E 0F. Revised the Analog Comparator Electrical Specifications including the ACMP Bandgap reference voltage values. Corrected a transposition in the DFN drawing no. Updated 3 09/2007 the ICS Characteristic table in the Electricals Appendix to include the ICS factory trim and reference the parameters t chapter ...
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Chapter List of Chapters Chapter 1 MC9RS08KA2 Series Device Overview ......................................... 15 Chapter 2 Pins and Connections ..................................................................... 17 Chapter 3 Modes of Operation ......................................................................... 21 Chapter 4 Memory............................................................................................. 25 Chapter 5 Resets, Interrupts, and General System Control.......................... 35 Chapter ...
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Section Number MC9RS08KA2 Series Device Overview 1.1 Overview .........................................................................................................................................15 1.2 MCU Block Diagram ......................................................................................................................15 1.3 System Clock Distribution ..............................................................................................................16 2.1 Introduction .....................................................................................................................................17 2.2 Device Pin Assignment ...................................................................................................................17 2.3 Recommended System Connections ...............................................................................................18 2.4 Pin Detail .........................................................................................................................................18 2.4.1 Power ..............................................................................................................................19 2.4.2 ...
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Section Number 4.6.4 Security ...........................................................................................................................31 4.7 Flash Registers and Control Bits .....................................................................................................32 4.7.1 Flash Options Register (FOPT and NVOPT) .................................................................32 4.7.2 Flash Control Register (FLCR) ......................................................................................33 4.8 Page Select Register (PAGESEL) ...................................................................................................33 Resets, Interrupts, and General System Control 5.1 Introduction ...
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Section Number 7.1.3 Block Diagram ................................................................................................................52 7.2 External Signal Description ............................................................................................................52 7.3 Register Definition ..........................................................................................................................53 7.3.1 KBI Status and Control Register (KBISC) .....................................................................53 7.3.2 KBI Pin Enable Register (KBIPE) .................................................................................54 7.3.3 KBI Edge Select Register (KBIES) ................................................................................54 7.4 Functional Description ...
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Section Number Internal Clock Source (RS08ICSV1) 9.1 Introduction .....................................................................................................................................75 9.1.1 Features ...........................................................................................................................76 9.1.2 Modes of Operation ........................................................................................................76 9.1.2.1 FLL Engaged Internal (FEI) ...........................................................................76 9.1.2.2 FLL Bypassed Internal (FBI) ..........................................................................76 9.1.2.3 FLL Bypassed Internal Low Power (FBILP) .................................................76 9.1.2.4 Stop (STOP) ...
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Section Number 11.1 Introduction .....................................................................................................................................89 11.1.1 Features ...........................................................................................................................90 11.1.2 Modes of Operation ........................................................................................................90 11.1.2.1 Operation in Wait Mode ..................................................................................90 11.1.2.2 Operation in Stop Modes ................................................................................90 11.1.2.3 Operation in Active Background Mode ..........................................................90 11.1.3 Block Diagram ................................................................................................................91 11.2 External Signal Description ...
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Section Number A.1 Introduction ...................................................................................................................................109 A.2 Absolute Maximum Ratings ..........................................................................................................109 A.3 Thermal Characteristics .................................................................................................................110 A.4 Electrostatic Discharge (ESD) Protection Characteristics ............................................................111 A.5 DC Characteristics .........................................................................................................................111 A.6 Supply Current Characteristics ......................................................................................................115 A.7 Analog Comparator (ACMP) Electricals ......................................................................................117 A.8 Internal Clock Source ...
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... CPU RS08 SYSTEM CONTROL RESET AND STOP WAKEUP MODES OF OPERATION POWER MANAGEMENT RTI COP WAKEUP LVD USER FLASH MC9RS08KA2 — 2048 BYTES MC9RS08KA1 — 1024 BYTES USER RAM — 63 BYTES INTERNAL CLOCK SOURCE (ICS POWER AND V INTERNAL REGULATOR DD Figure 1-1. MC9RS08KA2 Series Block Diagram ...
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Chapter 1 MC9RS08KA2 Series Device Overview Table 1-1 provides the functional versions of the on-chip modules. Analog Comparator (ACMP) Keyboard Interrupt (KBI) Modulo Timer (MTIM) Internal Clock Source (ICS) 1.3 System Clock Distribution ICSIRCLK ICSFFCLK ICS ICSOUT 1 The fixed ...
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Chapter 2 Pins and Connections 2.1 Introduction This chapter describes signals that connect to package pins. It includes a pinout diagram, a table of signal properties, and a detailed discussion of signals. 2.2 Device Pin Assignment Figure 2-1 and Figure ...
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Chapter 2 Pins and Connections PTA2/KBIP2/TCLK/RESET/V PP PTA3/ACMPO/BKGD/ Figure 2-3. MC9RS08KA2 Series in 8-Pin Narrow Body SOIC 2.3 Recommended System Connections Figure 2-4 shows reference connection for background debug and Flash programming BACKGROUND HEADER ...
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Power V and V are the primary power supply pins for the MCU. This voltage source supplies power to all I buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides a regulated lower-voltage ...
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Chapter 2 Pins and Connections cables and the absolute value of the internal pullup device play almost no role in determining rise and fall times on the BKGD pin. 2.4.4 General-Purpose I/O and Peripheral Ports The remaining pins are shared ...
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Chapter 3 Modes of Operation 3.1 Introduction This chapter describes the operating modes of the MC9RS08KA2 Series are described in this chapter. It also details entry into each mode, exit from each mode, and functionality while in each of the ...
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Chapter 3 Modes of Operation • When a BDC breakpoint is encountered After active background mode is entered, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user application program. ...
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Table 3-1 summarizes the behavior of the MCU in wait mode. Mode CPU Peripherals Wait Standby Optionally on 3.6 Stop Mode Stop mode is entered upon execution of a STOP instruction when the STOPE bit in the system option register ...
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Chapter 3 Modes of Operation the IREFSTEN bit. For the ICS to run in stop, the LVDE and LVDSE bits in the SPMSC1 must both be set before entering stop. 3.6.1 Active BDM Enabled in Stop Mode Entry into active ...
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... Other peripheral registers ($0200–$023F) • Nonvolatile memory — MC9RS08KA2: $3800–$3FFF — MC9RS08KA1: $3C00—$3FFF 1. Physical RAM in $000E can be accessed through the D[X] register when the content of the index register X is $0E. Freescale Semiconductor MC9RS08KA2 Series Data Sheet, Rev. 4 ...
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... HIGH PAGE REGISTERS $023F $E0 $3C00 $3FFB $3FFC $3FFD $3FFF MC9RS08KA2 Series Data Sheet, Rev. 4 PAGE REGISTER CONTENT $00 FAST ACCESS RAM 14 BYTES D[X] REGISTER X PAGESEL RAM 48 BYTES UNIMPLEMENTED PAGING WINDOW UNIMPLEMENTED $08 (reset value) UNIMPLEMENTED $F0 FLASH 1020 BYTES NVOPT FLASH MC9RS08KA1 Freescale Semiconductor ...
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Unimplemented Memory Attempting to access either data or an instruction at an unimplemented memory address will cause reset. 4.3 Indexed/Indirect Addressing Register D[X] and register X together perform the indirect data access. Register D[X] is mapped to address $000E. ...
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Chapter 4 Memory Frequently used registers can make use of the short addressing mode instructions for faster load, store, and clear operations. For short addressing mode instructions, the operand is encoded along with the opcode to a single byte. Address ...
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Address Register Name Bit 7 $020C– Unimplemented — $020F $0210 FOPT 0 $0211 FLCR 0 $0212– Reserved — $0213 $0214– Unimplemented — $021F — $0220 PTAPE 0 $0221 PTAPUD 0 $0222 PTASE 0 $0223– Unimplemented — $023F $3FF8 Reserved — ...
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Chapter 4 Memory • 1000 program/erase cycles at typical voltage and temperature • Security feature for Flash 4.6.2 Flash Programming Procedure Programming of Flash memory is done on a row basis. A row consists of 64 consecutive bytes ...
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Write any data to any Flash location, via the high page accessing window $00C0–$00FF. (Prior to the data writing operation, the PAGESEL register must be configured correctly to map the high page accessing window to the any Flash locations). ...
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Chapter 4 Memory When the device boots up to normal operating mode, where MS pin is high during reset, with SECD programmed (SECD = 0), Flash security is engaged. BKGDPE is reset to 0, and all BDM communication is blocked, ...
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Flash Control Register (FLCR Reset Unimplemented or Reserved Field 3 High Voltage Enable — This read/write bit enables high voltages to the Flash array for program and erase HVEN operations. ...
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Chapter 4 Memory Start address of memory block selected Figure 4-6. Memory Block Boundary Selector Table 4-5 shows the memory block to be accessed through paging window ($00C0–$00FF). Physical location $0000-$000E is RAM. Physical location $000F is register X. D[X] ...
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Chapter 5 Resets, Interrupts, and General System Control 5.1 Introduction This chapter discusses basic reset and interrupt mechanisms and the various sources of reset and interrupt in the MC9RS08KA2 Series. Some interrupt sources from peripheral modules are discussed in greater ...
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Chapter 5 Resets, Interrupts, and General System Control • Computer operating properly (COP) timer • Illegal opcode detect (ILOP) • Illegal address detect (ILAD) • Background debug forced reset via BDC command BDC_RESET Each of these sources, with the exception ...
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ACMP are still available to wake the CPU from wait or stop mode the responsibility of the user application to poll the corresponding module to determine the source of wakeup. Each wakeup source of the module is ...
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Chapter 5 Resets, Interrupts, and General System Control for applications requiring more accurate real-time interrupts. The RTICLKS bit in SRTISC is used to select the RTI clock source. Both the1-kHz and 32-kHz clock sources for the RTI can be used ...
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Field 7 Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was POR ramping up at the time, the low-voltage reset (LVR) status bit is also set to indicate that the reset occurred ...
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Chapter 5 Resets, Interrupts, and General System Control Field 7 COP Watchdog Enable — This write-once bit selects whether the COP watchdog is enabled. COPE 0 COP watchdog timer disabled. 1 COP watchdog timer enabled (force reset on timeout). 6 ...
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Table 5-4. SDIDH Register Field Descriptions Field 7:4 Revision Number — The high-order 4 bits of address SDIDH are hard coded to reflect the current mask set REV[3:0] revision number (0–F). 3:0 Part Identification Number — Each derivative in the ...
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Chapter 5 Resets, Interrupts, and General System Control Table 5-6. SRTISC Register Field Descriptions (continued) Field 4 Real-Time Interrupt Enable — This read-write bit enables real-time interrupts. RTIE 0 Real-time interrupts disabled. 1 Real-time interrupts enabled. 2:0 Real-Time Interrupt Delay ...
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System Power Management Status and Control 1 Register (SPMSC1) This high page register contains status and control bits to support the low voltage detect function, and to enable the bandgap voltage reference for use by the ACMP and the ...
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Chapter 5 Resets, Interrupts, and General System Control 5.8.6 System Interrupt Pending Register (SIP1) This high page register contains status of the pending interrupt from the modules Reset Unimplemented or Reserved ...
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Chapter 6 Parallel Input/Output Control This section explains software controls related to parallel input/output (I/O) and pin control. The MC9RS08KA2 Series has one parallel I/O port, which includes two I/O pins in the 6-pin package or four I/O pins in ...
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Chapter 6 Parallel Input/Output Control When a shared digital function is enabled for a pin, the output buffer is controlled by the shared function. However, the data direction register bit will continue to control the source for reads of the ...
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Field 5:0 Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A PTAD[5:0] pins that are configured as outputs, reads return the last value written to ...
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Chapter 6 Parallel Input/Output Control corresponding pulling device enable register bit. The pulling device is also disabled if the pin is controlled by an analog function Reset Figure 6-4. Internal Pulling Device ...
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R W Reset Figure 6-6. Slew Rate Enable for Port A Register (PTASE) Table 6-5. PTASE Register Field Descriptions Field 5:3;1:0 Output Slew Rate Enable for Port A Bits — Each of these control ...
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Chapter 6 Parallel Input/Output Control 50 MC9RS08KA2 Series Data Sheet, Rev. 4 Freescale Semiconductor ...
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Chapter 7 Keyboard Interrupt (RS08KBIV1) 7.1 Introduction The keyboard interrupt (KBI) module provides independently enabled external interrupt sources. RS08 CORE BDC CPU RS08 SYSTEM CONTROL RESET AND STOP WAKEUP MODES OF OPERATION POWER MANAGEMENT RTI COP WAKEUP LVD USER FLASH ...
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Chapter 7 Keyboard Interrupt (RS08KBIV1) 7.1.2 Modes of Operation This section defines the KBI operation in wait, stop, and background debug modes. 7.1.2.1 Operation in Wait Mode The KBI continues to operate in wait mode if enabled before executing the ...
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Register Definition The KBI includes three registers: • An 8-bit pin status and control register • An 8-bit pin enable register • An 8-bit edge select register Refer to the direct-page register summary in for all KBI registers. This ...
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Chapter 7 Keyboard Interrupt (RS08KBIV1) Table 7-3. KBISC Register Field Descriptions (continued) Field 1 Keyboard Interrupt Enable — KBIE enables keyboard interrupt requests. KBIE 0 Keyboard interrupt request not enabled. 1 Keyboard interrupt request enabled. 0 Keyboard Detection Mode — ...
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Functional Description This on-chip peripheral module is called a keyboard interrupt (KBI) module because it was originally designed to simplify the connection and use of row-column matrices of keyboard switches. However, these inputs are also useful as extra external ...
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Chapter 7 Keyboard Interrupt (RS08KBIV1) 5. Write to KBACK in KBISC to clear any false interrupts. 6. Set KBIE in KBISC to enable interrupts. 56 MC9RS08KA2 Series Data Sheet, Rev. 4 Freescale Semiconductor ...
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Chapter 8 Central Processor Unit (RS08CPUV1) 8.1 Introduction This chapter is a summary of information about the registers, addressing modes, and instruction set of the RS08 Family CPU. For a more detailed discussion, refer to the RS08 Core Reference Manual, ...
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Chapter 8 Central Processor Unit (RS08CPUV1 addition to the CPU registers, there are three memory mapped registers that are tightly coupled with the core address generation during data read and write operations. They are the indexed data ...
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Program Counter (PC) The program counter is a 14-bit register that contains the address of the next instruction or operand to be fetched. During normal execution, the program counter automatically increments to the next sequential memory location each time ...
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Chapter 8 Central Processor Unit (RS08CPUV1) Other instructions may be executed between the test and the conditional branch as long as the only instructions used are those which do not disturb the CCR bits that affect the conditional branch. For ...
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Page Select Register (PAGESEL) This 8-bit page select register allows the user to access all memory locations in the entire 16K-byte address space through a page window located from $00C0 to $00FF. This register resides at the memory mapped ...
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Chapter 8 Central Processor Unit (RS08CPUV1) expression in the operand field of the branch instruction; the assembler calculates the difference between the location counter (which points at the next address after the branch instruction at the time) and the address ...
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Short Addressing Mode (SRT) SRT addressing mode is capable of addressing only the first 32 bytes in the address map, from $0000 to $001F. This addressing mode is available for CLR, LDA, and STA instructions. A system can be ...
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Chapter 8 Central Processor Unit (RS08CPUV1) • Reset events force the CPU to start over at the beginning of the application program, which forces execution to start at $3FFD. • A host development system can cause the CPU to go ...
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Summary Instruction Table Instruction Set Summary Nomenclature The nomenclature listed here is used in the instruction descriptions in Operators ( ) = Contents of register or memory location shown inside parentheses ← loaded with (read: “gets”) ⇔ ...
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Chapter 8 Central Processor Unit (RS08CPUV1 Low-order eight bits of a direct address $0000–$00FF (high byte assumed to be $00 One byte of immediate data hh = High-order 6-bit of 14-bit extended address prefixed with 2-bit ...
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Table 8-1. Instruction Set Summary (Sheet Source Description Form ADC #opr8i ADC opr8a Add with Carry (1) ADC ,X ADC X ADD #opr8i ADD opr8a ADD opr4a Add without Carry (1) ADD ,X ADD X AND #opr8i ...
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Chapter 8 Central Processor Unit (RS08CPUV1) Table 8-1. Instruction Set Summary (Sheet Source Description Form Branch if Higher or Same (1) BHS rel (Same as BCC) Branch if Lower (Same (1) BLO rel as BCS) BNE rel ...
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Table 8-1. Instruction Set Summary (Sheet Source Description Form BRSET n,opr8a,rel BRSET n,D[X],rel Branch if Bit n in Memory Set BRSET n,X,rel BSET n,opr8a BSET n,D[X] Set Bit n in Memory BSET n,X 1. This is a ...
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Chapter 8 Central Processor Unit (RS08CPUV1) Table 8-1. Instruction Set Summary (Sheet Source Description Form BSR rel Branch Subroutine CBEQA #opr8i,rel CBEQ opr8a,rel Compare and Branch if (1),(2) CBEQ ,X,rel Equal (1) CBEQ X,rel CLC Clear Carry ...
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Table 8-1. Instruction Set Summary (Sheet Source Description Form (1) LDX #opr8i Load Index Register from (1) LDX opr8a Memory (1) LDX ,X LSLA Logical Shift Left LSRA Logical Shift Right MOV opr8a,opr8a MOV #opr8i,opr8a MOV D[X],opr8a ...
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Chapter 8 Central Processor Unit (RS08CPUV1) Table 8-1. Instruction Set Summary (Sheet Source Description Form SUB #opr8i SUB opr8a SUB opr4a Subtract (1) SUB ,X SUB X (1) TAX Transfer (1) TST opr8a (1) ...
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DIR DIR TNY DIR/REL HIGH LOW BRSET0 BSET0 INC BRA 3 DIR 2 DIR 1 TNY 2 REL BRCLR0 BCLR0 INC CBEQ CBEQA 3 DIR 2 ...
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Chapter 8 Central Processor Unit (RS08CPUV1) 74 MC9RS08KA2 Series Data Sheet, Rev. 4 Freescale Semiconductor ...
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... CPU RS08 SYSTEM CONTROL RESET AND STOP WAKEUP MODES OF OPERATION POWER MANAGEMENT RTI COP WAKEUP LVD USER FLASH MC9RS08KA2 — 2048 BYTES MC9RS08KA1 — 1024 BYTES USER RAM — 63 BYTES INTERNAL CLOCK SOURCE (ICS POWER AND V INTERNAL REGULATOR DD Figure 9-1. MC9RS08KA2 Series Block Diagram Highlighting ICS Block ...
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Internal Clock Source (RS08ICSV1) 9.1.1 Features Key features of the ICS module are: • Frequency-locked loop (FLL) is trimmable for accuracy — 0.2% resolution using internal 32 kHz reference — 2% deviation over voltage and temperature using internal 32 kHz ...
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IREFSTEN Internal Reference Clock (32 kHz) 9 TRIM 1 ICSOUT is two times the bus frequency Figure 9-2. Internal Clock Source (ICS) Block Diagram 9.2 External Signal Description No ICS signal connects off chip. 9.3 Register Definition Table 9-1 is ...
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Internal Clock Source (RS08ICSV1 CLKS W Reset Unimplemented Field 6 Clock Source Select — Selects the clock source that controls the bus frequency. The actual bus frequency CLKS depends on the value of ...
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ICS Trim Register (ICSTRM POR Reset Field 7:0 ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal TRIM reference clock period. The bits’ ...
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Internal Clock Source (RS08ICSV1) 9.4 Functional Description 9.4.1 Operational Modes The states of the ICS are shown as a state diagram and are described in this section. The arrows indicate the allowed movements between the states. CLKS=0 FLL Engaged Internal ...
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Stop ICS stop mode is entered whenever the MCU enters stop. In this mode, all ICS clocks are stopped except ICSIRCLK which will remaining running if IREFSTEN is written When the MCU is interrupted from stop, ...
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Internal Clock Source (RS08ICSV1) 9.4.6 Fixed Frequency Clock The ICS provides the ICSFFCLK output which can be used as an additional clock source to a peripheral such as a timer, when the ICS is in FEI. ICSFFCLK is not a ...
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... CPU RS08 SYSTEM CONTROL RESET AND STOP WAKEUP MODES OF OPERATION POWER MANAGEMENT RTI COP WAKEUP LVD USER FLASH MC9RS08KA2 — 2048 BYTES MC9RS08KA1 — 1024 BYTES USER RAM — 63 BYTES INTERNAL CLOCK SOURCE (ICS POWER AND V INTERNAL REGULATOR DD Figure 10-1. MC9RS08KA2 Series Block Diagram Highlighting ACMP Block and Pins ...
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Analog Comparator (RS08ACMPV1) 10.1.1 Features The ACMP has the following features: • Full rail-to-rail supply operation • Less than input offset • Less than hysteresis • Selectable interrupt on rising edge, falling edge, or ...
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Internal Bandgap Reference Voltage ACMP+ ACMP- Figure 10-2. Analog Comparator (ACMP) Block Diagram Freescale Semiconductor Internal Bus ACBGS Status and Control ACME Register ACO + Interrupt Control - Comparator MC9RS08KA2 Series Data Sheet, Rev. 4 Analog Comparator (RS08ACMPV1) ACMP INTERRUPT ...
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Analog Comparator (RS08ACMPV1) 10.2 External Signal Description The ACMP has two analog input pins, ACMP+ and ACMP–, and one digital output pin, ACMPO. Each of the input pins can accept an input voltage that varies across the full operating voltage ...
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Field 7 Analog Comparator Module Enable — ACME enables the ACMP module. ACME 0 ACMP not enabled. 1 ACMP is enabled. 6 Analog Comparator Bandgap Select — ACBGS is used to select between the internal bandgap reference ACBGS voltage or ...
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Analog Comparator (RS08ACMPV1) Comparator inputs are high impedence analog pins which are sensitive to noise. Noisy VDD and/or pin toggling adjacent to the analog inputs may cause the comparator offset/hysteresis performance to exceed the specified values. Maximum source impedence is ...
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... CPU RS08 SYSTEM CONTROL RESET AND STOP WAKEUP MODES OF OPERATION POWER MANAGEMENT RTI COP WAKEUP LVD USER FLASH MC9RS08KA2 — 2048 BYTES MC9RS08KA1 — 1024 BYTES USER RAM — 63 BYTES INTERNAL CLOCK SOURCE (ICS POWER AND V INTERNAL REGULATOR DD Figure 11-1. MC9RS08KA2 Series Block Diagram Highlighting MTIM Block and Pin ...
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Modulo Timer (RS08MTIMV1) 11.1.1 Features Timer system features include: • 8-bit up-counter — Free-running or 8-bit modulo limit — Software controllable interrupt on overflow — Counter reset bit (TRST) — Counter stop bit (TSTP) • Four software selectable clock sources ...
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Block Diagram The block diagram for the modulo timer module is shown BUSCLK XCLK TCLK SYNC MTIM INTERRUPT TOF REQUEST TOIE Figure 11-2. Modulo Timer (MTIM) Block Diagram 11.2 External Signal Description The MTIM includes one external signal, TCLK, ...
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Modulo Timer (RS08MTIMV1) Name R MTIMSC W R MTIMCLK W R MTIMCNT W R MTIMMOD W 11.3.1 MTIM Status and Control Register (MTIMSC) MTIMSC contains the overflow status flag and control bits which are used to configure the interrupt enable, ...
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MTIM Clock Configuration Register (MTIMCLK) MTIMCLK contains the clock select bits (CLKS) and the prescaler select bits (PS Reset Figure 11-4. MTIM Clock Configuration Register (MTIMCLK) Field 5:4 Clock Source Select ...
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Modulo Timer (RS08MTIMV1) Field 7:0 MTIM Count — These eight read-only bits contain the current value of the 8-bit counter. Writes have no effect to COUNT this register. Reset clears the count to $00. 11.3.4 MTIM Modulo Register (MTIMMOD) 7 ...
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Functional Description The MTIM is composed of a main 8-bit up-counter with an 8-bit modulo register, a clock source selector, and a prescaler block with nine selectable values. The module also contains software selectable interrupt logic. The MTIM counter ...
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Modulo Timer (RS08MTIMV1) 11.4.1 MTIM Operation Example This section shows an example of the MTIM operation as the counter reaches a matching value from the modulo register. selected clock source MTIM clock (PS=%0010) MTIMCNT $A7 TOF MTIMMOD: Figure 11-7. MTIM ...
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Chapter 12 Development Support 12.1 Introduction Development support systems in the RS08 family include the RS08 background debug controller (BDC). The BDC provides a single-wire debug interface to the target MCU. This interface provides a convenient means for programming the ...
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Chapter 12 Development Support • BDC_RESET command allows host to reset MCU without using a reset pin • One hardware address breakpoint built into BDC • RS08 clock source runs in stop mode if BDM enabled to allow debugging when ...
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Figure 12-2. Standard RS08 BDM Tool Connector Background debug controller (BDC) serial communications use a custom serial protocol that was first introduced on the M68HC12 Family of microcontrollers. This protocol requires that the host knows the communication clock rate, which ...
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Chapter 12 Development Support The BDC serial communication protocol requires the host to know the target BDC clock speed. Commands and data are sent most significant bit first (MSB-first BDC clock cycles per bit. The interface times out ...
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BDC CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN TARGET MCU SPEEDUP PULSE HIGH IMPEDANCE PERCEIVED START OF BIT TIME BKGD PIN Figure 12-4. BDC Target-to-Host Serial Bit Timing (Logic 1) Figure 12-5 shows the host receiving a logic 0 ...
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Chapter 12 Development Support BDC CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN TARGET MCU DRIVE AND SPEEDUP PULSE PERCEIVED START OF BIT TIME BKGD PIN Figure 12-5. BDM Target-to-Host Serial Bit Timing (Logic 0) 12.3.3 SYNC and Serial Communication ...
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Subsequent bits must occur within 512 BDC cycles of the last bit sent. 12.4 BDC Registers and Control Bits The BDC contains two non-CPU accessible registers: • The BDC status and control register (BDCSCR 8-bit register containing ...
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Chapter 12 Development Support Table 12-1. BDCSCR Register Field Descriptions (continued) Field 5 BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select) BKPTEN control bit and BDCBKPT match register ...
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A13 A12 W Any Reset = Unimplemented or Reserved Figure 12-7. BDC Breakpoint Match Register (BDCBKPT) 12.5 RS08 BDC Commands BDC commands are sent serially from a host computer ...
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Chapter 12 Development Support Active Background Command Mode/ Mnemonic Non-Intrusive SYNC Non-intrusive BDC_RESET Any CPU mode BACKGROUND Non-intrusive READ_STATUS Non-intrusive WRITE_CONTROL Non-intrusive READ_BYTE Non-intrusive READ_BYTE_WS Non-intrusive WRITE_BYTE Non-intrusive WRITE_BYTE_WS Non-intrusive READ_BKPT Non-intrusive WRITE_BKPT Non-intrusive Active background GO mode Active background ...
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Table 12-2. RS08 BDC Command Summary (continued) Active Background Command Mode/ Mnemonic Non-Intrusive Active background WRITE_A mode Active background READ_CCR_PC mode Active background WRITE_CCR_PC mode Active background READ_SPC mode Active background WRITE_SPC mode 1 The SYNC command is a special ...
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Chapter 12 Development Support 108 MC9RS08KA2 Series Data Sheet, Rev. 4 Freescale Semiconductor ...
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Appendix A Electrical Characteristics A.1 Introduction This chapter contains electrical and timing specifications. A.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in permanent ...
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Appendix A Electrical Characteristics A.3 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator ...
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Solving Equation A-1 and Equation A-2 where constant pertaining to the particular part. K can be determined from measuring P (at equilibrium) for a known T D obtained by solving equations 1 and 2 iteratively for any ...
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Appendix A Electrical Characteristics (Temperature Range = –40 to 85°C Ambient) Parameter Input low voltage (V > 2.3 V) (all digital inputs) DD Input low voltage (1.8 V ≤ V ≤ 2 (all digital inputs) Input hysteresis (all ...
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Freescale Semiconductor Figure 12-8. Typical IOH vs. VDD-VOH VDD = 5 V Figure 12-9. Typical IOH vs. VDD-VOH VDD = 3 V Figure 12-10. Typical IOH vs. VDD-VOH VDD = 1.8 V MC9RS08KA2 Series Data Sheet, Rev. 4 Appendix A ...
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Appendix A Electrical Characteristics Figure 12-13. Typical V 114 Figure 12-11. Typical I vs VDD = 5 V Figure 12-12. Typical I vs VDD = vs MC9RS08KA2 ...
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Figure 12-14. Typical V A.6 Supply Current Characteristics Parameter 3 Run supply current measured MHz) Bus 3 Run supply current measured 1.25 MHz) Bus Stop mode supply current Bandgap buffer adder from stop ...
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Appendix A Electrical Characteristics Table A-5. Supply Current Characteristics (continued) Parameter ACMP adder from stop (ACME = 1) RTI adder from stop 4 with 1-kHz clock source enabled RTI adder from stop with 32-kHz ICS internal clock source reference enabled ...
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Figure 12-15. Typical Run I A.7 Analog Comparator (ACMP) Electricals Table A-6. Analog Comparator Electrical Specifications Characteristic Supply voltage Analog input voltage Analog source impedance 1 Analog input offset voltage 1 Analog Comparator hysteresis Analog Comparator bandgap reference voltage 1 ...
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Appendix A Electrical Characteristics Table A-7. Internal Clock Source Specifications Characteristic Stop recovery time (FLL wakeup to previous acquired frequency) IREFSTEN=0 IREFSTEN=1 1 Data in typical column was characterized at 3.0 V and 5.0 V, 25° typical recommended ...
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A.10 FLASH Specifications This section provides details about program/erase times and program-erase endurance for the FLASH memory. For detailed information about program/erase operations, see Freescale Semiconductor t KBIPWS t KBIPW KBI Pin ...
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Appendix A Electrical Characteristics Characteristic Supply voltage for program/erase Program/Erase voltage V current PP Program Mass erase Supply voltage for read operation 0 < f < 10 MHz Bus Byte program time Mass erase time 2 Cumulative program HV time ...
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WRITE DATA PGM HVEN Next Data applies if programming multiple bytes in a single row, reference 2 V must valid operating voltage before voltage is applied or removed from the V DD ...
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Appendix A Electrical Characteristics MASS HVEN must valid operating voltage before voltage is applied or removed from the V DD 122 nvh1 nvs vps Figure ...
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... Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information This section contains ordering numbers for MC9RS08KA2 Series devices. See below for an example of the device numbering system. Device Number FLASH MC9RS08KA2 2 KB MC9RS08KA1 1 KB Status (MC = Fully Qualified) Memory (9 = FLASH-based) Core Family B.2 Mechanical Drawings This following pages contain mechanical specifications for MC9RS08KA2 Series package options: • ...
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Appendix B Ordering Information and Mechanical Drawings 124 MC9RS08KA2 Series Data Sheet, Rev. 4 Freescale Semiconductor ...
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How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter ...