MC9RS08KA1 FREESCALE [Freescale Semiconductor, Inc], MC9RS08KA1 Datasheet - Page 99

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MC9RS08KA1

Manufacturer Part Number
MC9RS08KA1
Description
RS08 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheets

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Chapter 12 Development Support
Figure 12-4
shows the host receiving a logic 1 from the target MCU. Because the host is asynchronous to
the target, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived
start of the bit time in the target. The host holds the BKGD pin low long enough for the target to recognize
it (at least two target BDC cycles). The host must release the low drive before the target drives a brief
active-high speedup pulse seven cycles after the perceived start of the bit time. The host should sample the
bit level approximately 10 cycles after it started the bit time.
BDC CLOCK
(TARGET MCU)
HOST DRIVE
HIGH IMPEDANCE
TO BKGD PIN
TARGET MCU
SPEEDUP PULSE
HIGH IMPEDANCE
HIGH IMPEDANCE
PERCEIVED START
OF BIT TIME
R-C RISE
BKGD PIN
10 CYCLES
EARLIEST START
OF NEXT BIT
10 CYCLES
HOST SAMPLES BKGD PIN
Figure 12-4. BDC Target-to-Host Serial Bit Timing (Logic 1)
MC9RS08KA2 Series Data Sheet, Rev. 2
Freescale Semiconductor
99

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