M3850 RENESAS [Renesas Technology Corp], M3850 Datasheet
M3850
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M3850 Summary of contents
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... Power dissipation In high-speed mode Except M38507F8AFP/SP ............................................. 32.5mW M38507F8AFP/SP ......................................................... 37.5mW (at 12.5 MHz oscillation frequency power source voltage) In low-speed mode Except M38507F8AFP/SP ................................................ M38507F8AFP/SP .......................................................... 450 W (at 32 kHz oscillation frequency power source voltage) 1(Clock-synchronized) Operating temperature range .................................... –20 to 85°C 1 ...
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Group (Spec.A) Fig. 2 Functional block diagram Rev.2.10 2005.11.14 page REJ03B0093-0210 ...
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Group (Spec.A) Table 1 Pin description Pin Name Power source CC SS CNV CNV input SS SS Reference voltage V REF Analog power AVss source RESET Reset input X Clock input IN X Clock output OUT ...
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... Group (Spec.A) PART NUMBERING Product name M3850 Fig. 3 Part numbering Rev.2.10 2005.11.14 page REJ03B0093-0210 A– XXX SP Package type SP : PRDP0042BA PRSP0042GA-B ROM number Omitted in flash memory version. – : standard Omitted in flash memory version. H–: Partial specification changed version A–: High-speed version ...
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... Mass production 8K M38503M2A 384 512 Fig. 4 Memory expansion plan Rev.2.10 2005.11.14 page REJ03B0093-0210 Packages PRDP0042BA-A ......................... 42-pin shrink plastic-molded DIP PRSP0042GA-B .................................. 42-pin plastic-molded SOP Mass production M38507M8A/F8A M38504M6A 640 768 896 1024 RAM size (bytes) 1152 1280 1408 1536 2048 ...
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... M38503M2A-XXXSP 8192 (8062) M38503M2A-XXXFP M38503M4A-XXXSP 16384 (16254) M38503M4A-XXXFP M38504M6A-XXXSP 24576 M38504M6A-XXXFP (24446) M38507F8ASP 32768 M38507F8AFP M38507M8A-XXXSP 32768 M38507M8A-XXXFP (32635) Table 3 Differences among 3850 group (standard), 3850 group (spec. H), and 3850 group (spec. A) 3850 group (standard) Serial interface 1: Serial I/O (UART or Clock-synchronized) A/D converter Unserviceable in low-speed mode Analog channel ...
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Group (Spec.A) FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 3850 group (spec. A) uses the standard 740 Family instruc- tion set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual ...
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Group (Spec. ...
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Group (Spec.A) [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch opera- tions ...
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Group (Spec.A) [CPU Mode Register (CPUM)] 003B The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B b 7 Fig. 7 Structure of CPU mode register Rev.2.10 2005.11.14 page ...
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Group (Spec.A) MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine ...
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Group (Spec.A) Port P0 (P0) 0000 16 Port P0 direction register (P0D) 0001 16 Port P1 (P1) 0002 16 Port P1 direction register (P1D) 0003 16 Port P2 (P2) 0004 16 Port P2 direction register (P2D) 0005 16 Port ...
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Group (Spec.A) I/O PORTS The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input ...
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Group (Spec.A) (1) Port P0 0 Pull-up control bit Direction register Port latch Data bus Serial I/O2 input (3) Port P0 2 Pull-up control bit P0 /S P-channel output disable bit 2 CLK2 Serial I/O2 synchronous clock selection bit ...
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Group (Spec. Pull-up control bit Serial I/O1 enable bit Direction register D a ...
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Group (Spec.A) Fig. 12 Port block diagram (3) Rev.2.10 2005.11.14 page REJ03B0093-0210 (17) Port ...
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Group (Spec. Fig. 13 Structure of port registers (1) Rev.2.10 2005.11.14 page REJ03B0093-0210 b0 Port P0, P1, P2 pull-up control register (PULL012: address 0012 ) 16 P0 pull-up control bit 0: No pull-up ...
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Group (Spec. Fig. 14 Structure of port registers (2) Rev.2.10 2005.11.14 page REJ03B0093-0210 ...
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Group (Spec.A) INTERRUPTS Interrupts occur by 15 sources among 15 sources: six external, eight internal, and one software. Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except ...
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Group (Spec.A) Table 7 Interrupt vector addresses and priority Vector Addresses (Note 1) Interrupt Source Priority High Reset (Note 2) 1 FFFD INT 0 2 FFFB Reserved 3 FFF9 INT 1 FFF7 4 INT 5 FFF5 2 INT / ...
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Group (Spec.A) Interrupt request bit Interrupt enable bit Interrupt disable flag (I) Fig. 15 Interrupt control ...
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Group (Spec.A) TIMERS The 3850 group (spec. A) has four timers: timer X, timer Y, timer 1, and timer 2. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value ...
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Group (Spec. ...
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Group (Spec.A) SERIAL INTERFACE SERIAL I/O1 Serial I/O1 can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer is also provided for baud rate generation ...
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Group (Spec.A) (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to “0”. Eight serial data transfer formats ...
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Group (Spec.A) Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output Receive buffer read signal ST Serial input Notes 1: Error flag detection occurs at the same time ...
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Group (Spec. ...
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Group (Spec.A) SERIAL I/O2 The serial I/O2 can be operated only as the clock synchronous type synchronous clock for serial transfer, either internal clock or external clock can be selected by the serial I/O2 synchronous clock selection ...
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Group (Spec.A) X CIN Main clock division ratio selection bits (Note “0” RDY2 “1” output enable bit output enable bit RDY2 RDY2 Serial I/O2 synchronous clock selection bit ...
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Group (Spec.A) S CMP2 S CLK2 S OUT2 S IN2 Fig output operation CMP2 Rev.2.10 2005.11.14 page REJ03B0093-0210 Judgment of I/O data comparison ...
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Group (Spec.A) PULSE WIDTH MODULATION (PWM) The 3850 group (spec. A) has a PWM function with an 8-bit resolution, based on a signal that is the clock input X clock input divided by 2. Data Setting The PWM output ...
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Group (Spec. ...
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Group (Spec.A) A/D CONVERTER [AD Conversion Registers (ADL, ADH)] 0035 , 0036 16 16 The AD conversion registers are read-only registers that store the result of an A/D conversion. Do not read these registers during an A/D conversion. [AD ...
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Group (Spec. ...
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Group (Spec.A) WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). The watchdog timer consists of an ...
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Group (Spec.A) RESET CIRCUIT To reset the microcomputer, RESET pin must be held at an “L” level for 20 cycles or more Then the RESET pin is returned “H” level (the power source ...
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Group (Spec. ...
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Group (Spec.A) CLOCK GENERATING CIRCUIT The 3850 group (spec. A) has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator be- tween X and X (X and X ). Use the circuit constants IN ...
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Group (Spec.A) [MISRG (MISRG)] 0038 16 MISRG consists of three control bits (bits for middle-speed mode automatic switch and one control bit (bit 0) for oscillation stabilizing time set after STP instruction released. By setting the ...
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Group (Spec.A) Reset Middle-speed mode CM ( MHz “1” MHz oscillating (32 kHz stopped) 4 Middle-speed mode CM (f( ) ...
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... Summary Table 8 lists the summary of the M38507F8A (flash memory ver- sion). The flash memory of the M38507F8 is divided into User ROM area and Boot ROM area as shown in Figure 47. In addition to the ordinary User ROM area to store the MCU op- eration control program, the flash memory has a Boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes ...
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... FFFD fixation). This mode is called the “Boot” mode. 16 Block Address Block addresses refer to the maximum address of each block. These addresses are used in the block erase command. In case of the M38507F8A, it has only one block. 8000 16 F000 Block kbyte FFFF FFFF ...
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Group (Spec.A) Outline Performance (CPU Rewrite Mode) CPU rewrite mode is usable in the single-chip or Boot mode. The only User ROM area can be rewritten in CPU rewrite mode. In CPU rewrite mode, the CPU erases, programs and ...
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Group (Spec. ...
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Group (Spec.A) Precautions on CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During CPU rewrite mode, set the internal clock frequency 6.25 MHz or ...
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Group (Spec.A) Software Commands (CPU Rewrite Mode) Table 9 lists the software commands. After setting the CPU Rewrite Mode Select Bit of the flash memory control register to “1”, execute a software command to specify an erase or program ...
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Group (Spec.A) Erase All Blocks Command (20 / writing the command code “20 ” in the first bus cycle and the 16 confirmation command code “20 ” in the second bus cycle that 16 follows, the operation ...
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Group (Spec.A) Status Register (SRD) The status register shows the operating status of the flash memory and whether erase operations and programs ended suc- cessfully or in error. It can be read in the following ways: (1) By reading ...
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Group (Spec.A) Full Status Check By performing full status check possible to know the execu- tion results of erase and program operations. Figure 52 shows a Read status register ...
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Group (Spec.A) Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of internal flash memory from being read out or rewritten easily, this MCU incorporates a ROM code protect function for use in parallel I/O mode and ...
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Group (Spec.A) ID Code Check Function (in Standard serial I/O mode) Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the pro- grammer is compared ...
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Group (Spec.A) (2) Parallel I/O Mode Parallel I/O mode is the mode which parallel output and input soft- ware command, address, and data required for the operations (read, program, erase, etc built-in flash memory. Use the ex- ...
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Group (Spec.A) (3) Standard serial I/O Mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, pro- gram, erase, etc.) the internal flash memory. This I/O is clock synchronized serial. ...
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Group (Spec.A) Table 11 Description of pin function (Standard Serial I/O Mode) Pin Name V ,V Power input CC SS CNV CNV SS SS Reset input RESET X Clock input IN X Clock output OUT AV Analog power supply ...
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Group (Spec.A) P4 /INT 4 P4 /INT USY P2 /CNTR CLK1 P2 TxD RxD RESET 1 ...
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Group (Spec.A) Software Commands (Standard Serial I/O Mode) Table 12 lists software commands. In standard serial I/O mode, erase, program and read are controlled by transferring software Table 12 Software commands (Standard serial I/O mode) Control command 1 Page ...
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Group (Spec.A) Page Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. S CLK1 RxD TxD S (BUSY) RDY1 ...
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Group (Spec.A) Clear Status Register Command This command clears the bits (SR4, SR5) which are set when the status register operation ends in error. When the “50 code is sent with the 1st byte, the aforementioned bits are cleared. ...
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Group (Spec.A) Erase All Blocks Command This command erases the contents of all blocks. Execute the erase all blocks command as explained here following. (1) Transfer the “A7 ” command code with the 1st byte. 16 (2) Transfer the ...
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Group (Spec.A) Download Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the “FA ” command code with the 1st byte. 16 (2) Transfer the program size ...
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Group (Spec.A) Version Information Output Command This command outputs the version information of the control pro- gram stored in the Boot ROM area. Execute the version information output command as explained here following. S CLK1 RxD TxD S (BUSY) ...
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Group (Spec.A) ID Check This command checks the ID code. Execute the boot ID check command as explained here following. S CLK1 F5 RxD TxD S (BUSY) RDY1 Fig. 63 Timing for ID check ID Code When the flash ...
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Group (Spec.A) Status Register (SRD) The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read ...
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Group (Spec.A) Status Register 1 (SRD1) The status register 1 indicates the status of serial communica- tions, results from ID checks and results from check sum comparisons. It can be read after the status register (SRD) by writ- ing ...
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Group (Spec.A) Full Status Check Results from executed erase and program operations can be known by running a full status check. Figure 65 shows a flowchart of the full status check and explains how to remedy errors which occur. ...
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... necessary to apply Vcc to S Fig. 66 Example circuit application for standard serial I/O mode Rev.2.10 2005.11.14 page REJ03B0093-0210 CLK1 S (BUSY) RDY1 M38507F8A CNVss pin only when reset is released. CLK1 ...
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Group (Spec.A) Flash memory Electrical characteristics Table 15 Absolute maximum ratings Symbol Parameter V Power source voltage CC Input voltage P0 – – REF V Input voltage ...
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Group (Spec.A) NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. Af- ter a reset, initialize flags which affect ...
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Group (Spec.A) NOTES ON USAGE Differences among 3850 group (standard), 3850 group (spec. H), and 3850 group (spec. A) (1) The absolute maximum ratings of 3850 group (spec. H/A) is smaller than that of 3850 group (standard). •Power source ...
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Group (Spec.A) Electrical characteristics Absolute maximum ratings Table 17 Absolute maximum ratings Symbol Parameter V Power source voltage CC Input voltage P0 – – REF Input voltage ...
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Group (Spec.A) Recommended operating conditions Table 18 Recommended operating conditions ( 2 – °C, unless otherwise noted Symbol V Power source voltage CC V Power source voltage SS ...
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Group (Spec.A) Table 19 Recommended operating conditions ( 2 – °C, unless otherwise noted) CC Symbol I “H” peak output current OH(peak) I “L” peak output current (Note 1) OL(peak) ...
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Group (Spec.A) Table 21 Electrical characteristics ( 2 – °C, unless otherwise noted Symbol Parameter V –V Hysteresis T+ T– CNTR , CNTR ...
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... M38507F8AFP/ 12.5 MHz (in WIT state stopped ) = 8 MHz (in WIT state stopped Except ) = stopped M38507F8AFP/ 32.768 kHz M38507F8FP/SP Except ) = stopped M38507F8AFP/ 32.768 kHz (in WIT state) M38507F8AFP/ Except stopped M38507F8AFP/ 32.768 kHz M38507F8AFP/ Except stopped M38507F8AFP/ 32.768 kHz (in WIT state) M38507F8AFP/ MHz ° ...
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Group (Spec.A) A/D converter characteristics Table 23 A/D converter characteristics (V = 2 Symbol Parameter – Resolution – Absolute accuracy (excluding quantization error) t Conversion time ...
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Group (Spec.A) Timing requirements Table 24 Timing requirements ( 4 – °C, unless otherwise noted Symbol Reset input “L” pulse width t (RESET) ...
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Group (Spec.A) Switching characteristics Table 26 Switching characteristics ( 4 – °C, unless otherwise noted Symbol CLK1 Serial I/O1 ...
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Group (Spec.A) Measurement output pin Fig. 68 Circuit for measuring output switching characteristics Rev.2.10 2005.11.14 page REJ03B0093-0210 100 pF ...
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Group (Spec. ...
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Group (Spec.A) PACKAGE OUTLINE JEITA Package Code RENESAS Code P-SDIP42-13x36.72-1.78 PRDP0042BA SEATING PLANE e JEITA Package Code RENESAS Code P-SSOP42-8.4x17.5-0.80 PRSP0042GA Index mark * Rev.2.10 2005.11.14 page REJ03B0093-0210 ...
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Group (Spec.A) APPENDIX NOTES ON PROGRAMMING 1. Processor status register (1) Initializing of processor status register Flags which affect program execution must be initialized after a reset. In particular essential to initialize the T and D flags ...
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Group (Spec.A) NOTES ON PERIPHERAL FUNCTIONS Notes on input and output ports 1. Notes in standby state *1 In standby state , do not make input levels of an I/O port “unde- fined”, especially for I/O ports of the ...
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Group (Spec.A) Notes on Interrupts 1. Change of relevant register settings When the setting of the following registers or bits is changed, the interrupt request bit may be set to “1”. When not requiring the in- terrupt occurrence synchronized ...
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Group (Spec.A) 2. Notes when selecting clock asynchronous serial I/O (Serial I/O1) (1) Stop of transmission operation Clear the transmit enable bit to “0” (transmit disabled). <Reason> Since transmission is not stopped and the transmission circuit is not initialized ...
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Group (Spec.A) Notes on A/D converter 1. Analog input pin Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0. Further, be sure to ...
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Group (Spec.A) Notes on restarting oscillation • Restarting oscillation Usually, when the MCU stops the clock oscillation by STP instruc- tion and the STP instruction has been released by an external interrupt source, the fixed values of Timer 1 ...
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REVISION HISTORY Rev. Date Page 1.00 – First edition issued Jun. 10, 2004 2.00 1, 4-6 Package name is revised. 42P4B Sep. 01, 2005 3 Table 1 Pin description is partly revised. 5 GROUP EXPANSION is revised. 16 Fig. 12 ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...