M3850 RENESAS [Renesas Technology Corp], M3850 Datasheet - Page 39

• Manufacturer Part Number: M3850
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
• Manufacturer: RENESAS [Renesas Technology Corp]

3850 Group (Spec.A)
[MISRG (MISRG)] 0038
MISRG consists of three control bits (bits 1 to 3) for middle-speed
mode automatic switch and one control bit (bit 0) for oscillation
stabilizing time set after STP instruction released.
By setting the middle-speed mode automatic switch start bit to “1”
while operating in the low-speed mode and setting the middle-
speed mode automatic switch set bit to “1”, X
automatically starts and the mode is automatically switched to the
middle-speed mode.
Fig. 45 System clock generating circuit block diagram (Single-chip mode)
Rev.2.10
REJ03B0093-0210
2005.11.14
Notes 1: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
Interrupt disable flag l
Interrupt request
2: f(X
3: When bit 0 of MISRG = “0”, the prescaler 12 is set to "FF
4: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions.
When low-speed mode is selected, set port Xc switch bit (b4) to “1”.
before executing the STP instruction is supplied as the count source at executing STP instruction.
When bit 0 of MISRG = “1”, set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to
the prescaler 12 and timer 1.
X
CIN
page 39 of 86
IN
X
)/16 is supplied as the count source to the prescaler 12 at reset, the count source
IN
16
Q
(Note 4)
S
R
Reset
X
“1”
COUT
X
STP instruction
OUT
Port X
switch bit
“0”
Main clock stop bit
High-speed or
middle-speed
mode
C
Main clock division ratio
selection bits (Note 1)
Low-speed mode
IN
oscillation
WIT instruction
1/2
low-speed mode
High-speed or
1/4
R
S
1/2
Fig. 44 Structure of MISRG
Q
16
Main clock division ratio
selection bits (Note 1)
Middle-speed mode
" and timer 1 is set to "01
b7
Note: When the mode is automatically switched from the low-speed mode to
Timer 12 count
source selection
bit
the middle-speed mode, the value of CPU mode register (address 003B
changes.
Q
S
R
Prescaler 12
STP instruction
Timing
b0
16
(Note 3)
".
MISRG
(MISRG : address 0038
Oscillation stabilizing time set after STP instruction
released bit
0: Automatically set “01
1: Automatically set nothing
Middle-speed mode automatic switch set bit
0: Not set automatically
1: Automatic switching enable
Middle-speed mode automatic switch wait time set bit
0: 6.5 to 7.5 machine cycles
1: 4.5 to 5.5 machine cycles
Middle-speed mode automatic switch start bit
(Depending on program)
0: Invalid
1: Automatic switch start
Not used (return “0” when read)
“FF
(internal clock)
16
Timer 1
” to Prescaler 12
Reset or
STP instruction
(Note 2)
Reset
16
16
)
” to Timer 1,
16
)