LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 15

• Manufacturer Part Number: LM3S6611-IQC20-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

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Synchronous Serial Interface (SSI) ............................................................................................ 295
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Inter-Integrated Circuit (I
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October 09, 2007
UART Line Control (UARTLCRH), offset 0x02C ............................................................... 271
UART Control (UARTCTL), offset 0x030 ......................................................................... 273
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 275
UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 277
UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 279
UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 280
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 281
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 283
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 284
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 285
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 286
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 287
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 288
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 289
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 290
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 291
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 292
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 293
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 294
SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 307
SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 309
SSI Data (SSIDR), offset 0x008 ...................................................................................... 311
SSI Status (SSISR), offset 0x00C ................................................................................... 312
SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 314
SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 315
SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 317
SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 318
SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 319
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 320
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 321
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 322
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 323
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 324
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 325
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 326
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 327
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 328
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 329
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 330
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 331
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C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 346
C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 347
C Master Data (I2CMDR), offset 0x008 ......................................................................... 351
C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 352
C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 353
C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 354
2
C) Interface ........................................................................................ 332
Preliminary
LM3S6611 Microcontroller
15