LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 429

• Manufacturer Part Number: LM3S6611-IQC20-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

October 09, 2007
Pin Name
I2C0SCL
I2C0SDA
I2C1SCL
I2C1SDA
GNDPHY
GNDPHY
GNDPHY
GNDPHY
GNDA
GNDA
LED0
LED1
MDIO
OSC0
OSC1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HIB
LDO
PA0
PA1
PA2
PA3
Pin Number
33
39
45
54
57
63
69
82
87
94
97
41
42
85
86
51
70
71
34
35
59
60
58
48
49
26
27
28
29
4
7
Preliminary
Pin Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
I
I
I
I
I
Buffer Type
Analog
Analog
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
OD
OD
OD
OD
Description
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
GND of the Ethernet PHY
GND of the Ethernet PHY
GND of the Ethernet PHY
GND of the Ethernet PHY
An output that indicates the processor is in
hibernate mode.
I2C module 0 clock
I2C module 0 data
I2C module 1 clock
I2C module 1 data
Low drop-out regulator output voltage. This
pin requires an external capacitor between
the pin and GND of 1 µF or greater. When the
on-chip LDO is used to provide power to the
logic, the LDO pin must also be connected to
the VDD25 pins at the board level in addition
to the decoupling capacitor(s).
MII LED 0
MII LED 1
MDIO of the Ethernet PHY
Main oscillator crystal input or an external
clock reference input.
Main oscillator crystal output.
GPIO port A bit 0
GPIO port A bit 1
GPIO port A bit 2
GPIO port A bit 3
LM3S6611 Microcontroller
429