LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 385
LM3S6611-IQC20-A0T
Manufacturer Part Number
LM3S6611-IQC20-A0T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S6611-IQC20-A0T.pdf
(477 pages)
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Ethernet MAC Individual Address 1 (MACIA1)
Base 0x4004.8000
Offset 0x018
Type R/W, reset 0x0000.0000
October 09, 2007
Reset
Reset
Type
Type
Bit/Field
31:16
15:8
7:0
R/W
RO
31
15
0
0
Register 8: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018
This register enables software to program the last two bytes of the hardware MAC address of the
Network Interface Card (NIC). (The first four bytes are in MACIA0). The 6-byte IAR is compared
against the incoming Destination Address fields to determine whether the frame should be received.
R/W
RO
30
14
0
0
MACOCT6
MACOCT5
reserved
Name
R/W
RO
29
13
0
0
R/W
RO
28
12
0
0
MACOCT6
R/W
RO
Type
27
11
R/W
R/W
0
0
RO
R/W
RO
26
10
0
0
Reset
0x0
0x0
0x0
R/W
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MAC Address Octet 6
The MACOCT6 bits represent the sixth octet of the MAC address used
to uniquely identify each Ethernet Controller.
MAC Address Octet 5
The MACOCT5 bits represent the fifth octet of the MAC address used to
uniquely identify each Ethernet Controller.
R/W
RO
24
0
8
0
reserved
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
MACOCT5
LM3S6611 Microcontroller
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
R/W
RO
17
0
1
0
R/W
RO
16
0
0
0
385
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