TSC80251-SK TEMIC [TEMIC Semiconductors], TSC80251-SK Datasheet - Page 14

• Manufacturer Part Number: TSC80251-SK
• Description: 8/16-bit Microcontroller with Serial Communication Interfaces
• Manufacturer: TEMIC [TEMIC Semiconductors]

TSC80251G2D
6.4 Configuration Bytes
The TSC80251G2D derivatives provide user design flexibility by configuring certain operating features at device
reset. These features fall into the following categories:
Two user configuration bytes UCONFIG0 (see Figure 7) and UCONFIG1 (see Figure 8) provide the information.
When EA# is tied to a low level, the configuration bytes are fetched from the external address space. The
TSC80251G2D derivatives reserve the top eight bytes of the memory address space (FF:FFF8h-FF:FFFFh) for an
external 8-byte configuration array. Only two bytes are actually used: UCONFIG0 at FF:FFF8h and UCONFIG1
at FF:FFF9h.
For the mask ROM devices, configuration information is stored in on-chip memory (see ROM Verifying). When
EA# is tied to a high level, the configuration information is retrieved from the on-chip memory instead of the
external address space and there is no restriction in the usage of the external memory.
UCONFIG0
Configuration Byte 0
Notes:
1. UCONFIG0 is fetched twice so it can be properly read both in Page or Non-Page modes. If P2.1 is cleared during the first data fetch, a
2. This selection provides compatibility with the standard 80C51 hardware which is multiplexing the address LSB and the data on Port 0.
14
Bit Number
Page mode configuration is used, otherwise the subsequent fetches are performed in Non-Page mode.
7
-
external memory interface (Page mode, address bits, programmed wait states and the address range for RD#,
WR#, and PSEN#)
source mode/binary mode opcodes
selection of bytes stored on the stack by an interrupt
mapping of the upper portion of on-chip code memory to region 00:
7
6
5
4
3
2
1
0
Bit Mnemonic
WSA1#
WSA1#
WSA0#
XALE#
PAGE#
6
RD1
RD0
SRC
-
Reserved
Wait State A bits
Extend ALE bit
Memory Signal Select bits
Page Mode Select bit
Source Mode/Binary Mode Select bit
WSA0#
Set this bit when writing to UCONFIG0.
Select the number of wait states for RD#, WR# and PSEN# signals for external memory accesses
(all regions except 01:).
Clear to extend the duration of the ALE pulse from T
Set to minimize the duration of the ALE pulse to 1·T
Specify a 18-bit, 17-bit or 16-bit external address bus and the usage of RD#, WR# and PSEN#
signals (see Table 13).
Clear to select the faster Page mode with A15:8/D7:0 on Port 2 and A7:0 on Port 0.
Set to select the non-Page mode
Clear to select the binary mode.
Set to select the source mode.
5
WSA1#
0
0
1
1
Figure 7. Configuration Byte 0
WSA0#
XALE#
0
1
0
1
(1)
4
Number of Wait States
(2)
RD1
3
with A15:8 on Port 2 and A7:0/D7:0 on Port 0.
3
2
1
0
Description
RD0
2
OSC
OSC
.
to 3·T
OSC.
PAGE#
1
Rev. A - May 7, 1999
SRC
0