TSC80251-SK TEMIC [TEMIC Semiconductors], TSC80251-SK Datasheet - Page 19

• Manufacturer Part Number: TSC80251-SK
• Description: 8/16-bit Microcontroller with Serial Communication Interfaces
• Manufacturer: TEMIC [TEMIC Semiconductors]

TSC80251G2D
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
Notes:
1. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
2. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
3. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
19
Increment
Increment
Decrement
Decrement
INC
DEC
INC
DEC
INC
DEC
INC
Compare
CMP
Mnemonic
Mnemonic
A
Rn
dir8
@Ri
Rm, #short
WRj, #short
DRk, #short
DRk, #short
DPTR
Rmd, Rms
WRjd, WRjs
DRkd, DRks
Rm, #data
WRj, #data16
DRk, #0data16
DRk, #1data16
Rm, dir8
WRj, dir8
Rm, dir16
WRj, dir16
Rm, @WRj
Rm, @DRk
<dest>, <src>
<dest>, <src>
Table 21. Summary of Increment and Decrement Instructions
(1)
(2)
INC <dest>
INC <dest>, <src>
DEC <dest>
DEC <dest>, <src>
CMP <dest>, <src>
ACC by 1
Register by 1
Direct address (on-chip RAM or SFR) by 1
Indirect address by 1
Byte register by 1, 2, or 4
Word register by 1, 2, or 4
Double word register by 1, 2, or 4
Double word register by 1, 2, or 4
Data pointer by 1
Register with register
Word register with word register
Dword register with dword register
Register with immediate data
Word register with immediate 16-bit data
Dword register with zero-extended 16-bit immediate data
Dword register with one-extended 16-bit immediate data
Direct address (on-chip RAM or SFR) with byte register
Direct address (on-chip RAM or SFR) with word register
Direct address (64K) with byte register
Direct address (64K) with word register
Indirect address (64K) with byte register
Indirect address (16M) with byte register
Table 22. Summary of Compare Instructions
Comments
Comments
dest opnd
dest opnd
dest opnd
dest opnd
dest opnd - src opnd
dest opnd + 1
dest opnd + src opnd
dest opnd - 1
dest opnd - src opnd
Bytes
Bytes
Binary Mode
Binary Mode
1
1
2
1
3
3
3
3
1
3
3
3
4
5
5
5
4
4
5
5
4
4
States
States
2
3
3
4
3
4
1
1
3
2
2
4
5
1
2
3
5
3
4
6
6
4
(2)
(1)
(2)
(3)
(2)
(2)
Rev. A - May 7, 1999
Bytes
Bytes
Source Mode
Source Mode
1
2
2
2
2
2
2
2
1
2
2
2
3
4
4
4
3
3
4
4
3
3
States
States
2
2
2
3
2
3
1
2
4
1
1
3
4
1
1
2
4
2
3
5
5
3
(2)
(1)
(2)
(3)
(2)
(2)