TSC80251-SK TEMIC [TEMIC Semiconductors], TSC80251-SK Datasheet - Page 27

• Manufacturer Part Number: TSC80251-SK
• Description: 8/16-bit Microcontroller with Serial Communication Interfaces
• Manufacturer: TEMIC [TEMIC Semiconductors]

TSC80251G2D
27
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. In internal execution only, add 1 to the number of states if the destination address is internal and odd.
3. Add 2 to the number of states if the destination address is external.
4. Add 3 to the number of states if the destination address is external.
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. In internal execution only, add 1 to the number of states if the destination/return address is internal and odd.
3. Add 2 to the number of states if the destination address is external.
4. Add 5 to the number of states if INTR= 1.
Absolute jump
Extended jump
Long jump
Short jump
Jump indirect
No operation
AJMP
EJMP
LJMP
SJMP
JMP
NOP
Absolute call
Extended call
Long call
Return from subroutine
Extended return from subroutine
Return from interrupt
Trap interrupt
ACALL
ECALL
LCALL
RET
ERET
RETI
TRAP
Mnemonic
Mnemonic
addr11
addr24
@DRk
@WRj
addr16
rel
@A +DPTR
addr11
@DRk
addr24
@WRj
addr16
<dest>, <src>
<dest>, <src>
Table 33. Summary of unconditional Jump Instructions
(1)
(1)
Table 34. Summary of Call and Return Instructions
AJMP <src>
EJMP <src>
LJMP <src>
SJMP rel
JMP @A +DPTR
NOP
ACALL <src>
ECALL <src>
LCALL <src>
RET
ERET
RETI
TRAP
Absolute jump
Extended jump
Extended jump (indirect)
Long jump (indirect)
Long jump (direct address)
Short jump (relative address)
Jump indirect relative to the DPTR
No operation (Jump never)
Absolute subroutine call
Extended subroutine call (indirect)
Extended subroutine call
Long subroutine call (indirect)
Long subroutine call
Return from subroutine
Extended subroutine return
Return from interrupt
Jump to the trap interrupt vector
Comments
Comments
(PC)
(PC)
(PC)
(PC)
(PC)
(PC)
(PC)
(PC)
(PC)
(PC)
(PC)
(PC)
pop (PC)
pop (PC)
IF [INTR= 0] THEN pop (PC)
IF [INTR= 1] THEN pop (PC)
(PC)
IF [INTR= 0] THEN push (PC)
IF [INTR= 1] THEN push (PSW1); push (PC)
23:16
10:0
23:0
15:0
(PC) +2; (PC)
(PC) + size (instr); (PC)
(PC) + size (instr); (PC)
(PC) +2; (PC)
(PC) +1
(PC) +2; push (PC)
(PC) + size (instr); push (PC)
(PC) + size (instr); push (PC)
(PC) + size (instr);
15:0
23:0
src opnd
src opnd
src opnd
FFh; (PC)
Bytes
Bytes
Binary Mode
Binary Mode
2
5
3
3
3
2
1
1
2
3
5
3
3
1
3
1
2
10:0
15:0
Rev. A - May 7, 1999
States
States
14
14
10
3
6
7
6
5
4
5
9
9
7
(PC) +rel
12
7
9
(2)(3)
(2)(4)
(2)(4)
(2)(4)
(2)(4)
(2)(4)
(2)(4)
(2)(3)
(2)(3)
(2)(4)
15:0
(2)(3)
(2)(3)
(2)(3)
1
(2)
(2)
(4)
src opnd
(A) + (DPTR)
15:0
23:0
;
15:0
23:0
15:0
; pop (PSW1)
Bytes
Bytes
Source Mode
Source Mode
23:0
15:0
2
4
2
2
3
2
1
1
2
2
4
2
3
1
2
1
1
src opnd
src opnd
;
;
23:0
States
States
13
13
3
5
6
5
5
4
5
9
9
9
7
11
7
8
(2)(3)
(2)(4)
(2)(4)
(2)(4)
(2)(4)
(2)(4)
(2)(4)
(2)(3)
(2)(3)
(2)(3)
(2)(4)
(2)(3)
(2)(3)
1
(2)
(2)
(4)