LF3304QC12 LODEV [LOGIC Devices Incorporated], LF3304QC12 Datasheet - Page 3

• Manufacturer Part Number: LF3304QC12
• Description: Dual Line Buffer/FIFO
• Manufacturer: LODEV [LOGIC Devices Incorporated]

DEVICES INCORPORATED
RWB — Reset Write B
See RWA Description.
RRB — Reset Read B
See RRA description.
OEA — Output Enable A
When OEA is LOW, AOUT
enabled for output. When OEA is
HIGH, AOUT
impedence state.
OEB — Output Enable B
When OEB is LOW, BOUT
enabled for output. When OEB is
HIGH, BOUT
impedence state.
Outputs
AOUT
AOUT
data output port.
BOUT
BOUT
data output port.
FIFO MODE
SIGNAL DEFINITIONS
Power
V
+3.3 V power supply. All pins must be
connected.
T
ADDRA
CC
ABLE
and GND
0
1
x
x
11-0
11-0
11-0
11-0
2. L
— Data Output B
is the 12-bit registered
— Data Output A
is the 12-bit registered
ADDRB
11-0
11-0
OADING
0
1
x
x
is placed in a high-
is placed in a high-
P
LDA
ROGRAMMABLE
0
0
x
x
11-0
11-0
is
is
LDB
0
0
x
x
F
Clocks
WCLKA — Write Clock A
Data present on AIN
into the LF3304 on the rising edge of
WCLKA when the device is configured
for writing.
RCLKA — Read Clock A
Data is read from the LF3304 and
presented on the output port (AOUT
after t
edge of RCLKA when the device is
configured for reading and the output
port is enabled. WCLKA and RCLKA
can be tied together and driven by the
same external clock or they may be
controlled by separate external clocks.
WCLKB — Write Clock B
Data present on BIN
the LF3304 on the rising edge of
WCLKB when the device is configured
for writing.
RCLKB — Read Clock B
Data is read from the LF3304 and
presented on the output port (BOUT
after t
edge of RCLKB when the device is
configured for reading and the output
port is enabled. WCLKB and RCLKB
can be tied together and driven by the
same external clock or they may be
controlled by separate external clocks.
Inputs
AIN
AIN
input port.
LAG
WCLKA
11-0
x
x
11-0
R
D
D
EGISTERS
has elapsed from the rising
has elapsed from the rising
— Data Input A
is the 12-bit registered data
WCLKB
x
x
3
11-0
11-0
Operation
PAEA Register
PAFA Register
PAEB Register
PAFB Register
is written into
is written
11-0
11-0
)
)
BIN
BIN
input port.
ADDRA — Address A
If LDA is LOW, on the rising edge of
WCLKA data present on AIN
written into the PAFA or PAEA register
depending on ADDRA (see Table 2).
The LSB, AIN
of PAFA and PAEA registers. The MSB,
AIN
and PAEA registers.
ADDRB — Address B
If LDB is LOW, on the rising edge of
WCLKB data present on BIN
written into the PAFB or PAEB register
depending on ADDRB (see Table 2).
The LSB, BIN
of PAFB and PAEB registers. The MSB,
BIN
and PAEB registers.
MODE
The mode select inputs determine the
operating mode of the LF3304 (Table 1) for
data being input on the next clock cycle.
When switching between modes, the
internal pipeline latencies of the device
must be observed. After switching
operating modes, either the user must
allow enough clock clycles to pass to flush
the internal RAM Array or RWx and RRx
must be driven LOW together before valid
data will appear on the outputs.
LENGTH — Non-Flag Pins
In FIFO Mode, the unused LENGTH pins
(LENGTH
LENGTH
Controls
LDA — RAM Array A Load
When LDA is LOW, data on AIN
latched in the LF3304 on the rising edge
of WCLKA.
Video Imaging Products
11-0
11
11-0
11
Dual Line Buffer/FIFO
, corresponds to the MSB of PAFB
, corresponds to the MSB of PAFA
1-0
— Data Input B
is the 12-bit registered data
4
— Mode Select
11
) must be tied LOW.
, LENGTH
0
0
, corresponds to the LSB
, corresponds to the LSB
10
, LENGTH
08/16/2000–LDS.3304-F
LF3304
11-0
11-0
is
11-0
is
5
,
is