XR16C850CJ EXAR [Exar Corporation], XR16C850CJ Datasheet - Page 27

• Manufacturer Part Number: XR16C850CJ
• Manufacturer: EXAR [Exar Corporation]

Logic 1 = Enable the receiver ready interrupt. The
receiver ready interrupt is cleared when LSR is read.
IER BIT-1:
Logic 0 = Disable the transmitter empty interrupt.
(normal default condition)
Logic 1 = Enable the transmitter empty interrupt. The
transmitter empty interrupt is cleared when ISR is read.
IER BIT-2:
Logic 0 = Disable the receiver line status interrupt.
(normal default condition)
Logic 1 = Enable the receiver line status interrupt. The
receiver line interrupt is cleared when LSR is read.
IER BIT-3:
Logic 0 = Disable the modem status register interrupt.
(normal default condition)
Logic 1 = Enable the modem status register interrupt.
The modem status interrupt is cleared when MSR is
read.
IER BIT -4:
Logic 0 = Disable sleep mode. (normal default condi-
tion)
Logic 1 = Enable sleep mode. See Sleep Mode section
for details.
IER BIT-5:
Logic 0 = Disable the software flow control, receive Xoff
interrupt. (normal default condition)
Logic 1 = Enable the software flow control, receive Xoff
interrupt. The Xoff interrupt is cleared by reading the ISR
register or upon receiving a Xon character. Also, when
Special Character mode is enabled (EFR-bit 5 =1)
reading the ISR register or a following received character
will cleared the interrupt. See Software Flow Control
section for details.
IER BIT-6:
Logic 0 = Disable the RTS interrupt. (normal default
condition)
Logic 1 = Enable the RTS interrupt. The 850 issues an
interrupt when the RTS pin transitions from a logic 0 to
a logic 1 as reported in MSR bit-register. The interrupt
is cleared by reading the MSR register.
Rev. 1.20
27
IER BIT-7:
Logic 0 = Disable the CTS interrupt. (normal default
condition)
Logic 1 = Enable the CTS interrupt. The 850 issues an
interrupt when CTS pin transitions from a logic 0 to a
logic 1 as reported in MSR register. The interrupt is
cleared by reading the MSR register.
FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the
FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are
defined as follows:
DMA MODE
transmit or receive operation, and is similar to the
ST16C450 mode. Transmit Ready (-TXRDY) will go to a
logic 0 when ever an empty transmit space is available
in the Transmit Holding Register (THR). Receive Ready
(-RXRDY) will go to a logic 0 whenever the Receive
Holding Register (RHR) is loaded with a character.
mode operation. The transmit interrupt is set when the
transmit FIFO is below the programmed trigger level. -
TXRDY remains a logic 0 as long as one empty FIFO
location is available. The receive interrupt is set when
the receive FIFO fills to the programmed trigger level.
However the FIFO continues to fill regardless of the
programmed level until the FIFO is full. -RXRDY remains
a logic 0 as long as the FIFO fill level is above the
programmed trigger level.
FCR BIT-0:
Logic 0 = Disable the transmit and receive FIFO.
(normal default condition)
Logic 1 = Enable the transmit and receive FIFO. This bit
must be a “1” when other FCR bits are written to or they
will not be programmed.
FCR BIT-1:
Logic 0 = No FIFO receive reset. (normal default
condition)
Logic 1 = Clears the FIFO counter and resets the
pointers logic (the receive shift register is not cleared or
altered). This bit will return to a logic 0 after clearing the
FIFO.
Mode 0
Mode 1
Set and enable the interrupt for each single
Set and enable the interrupt in a block
XR16C850