XR88C92CJ EXAR [Exar Corporation], XR88C92CJ Datasheet - Page 6
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XR88C92CJ
Manufacturer Part Number
XR88C92CJ
Description
DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
Manufacturer
EXAR [Exar Corporation]
Datasheet
1.XR88C92CJ.pdf
(32 pages)
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XR88C92/192
SYMBOL DESCRIPTION (* 44 pin TQFP)
IP3
IP4
IP5
IP6
-CS
D0-D7
-IOW
-IOR
VCC
N.C.
Symbol
Rev. 1.31
28,18
27,19
26,20
25,21
23,34
1,12
44
43
42
41
39
10
44
3
9
25,16
24,17
23,18
22,19
Pin
40
39
38
37
35
40
2
8
9
22,12
21,13
20,14
19,15
38,39
11,23
44*
41
37
36
35
33
3
4
Signal
type
Pwr
I/O
I
I
I
I
I
I
I
Multi-purpose input or Channel A transmit external clock port
input. The transmit data is clocked on the falling edge of the
clock.
Multi-purpose input or Channel A receive external clock input.
The transmit data is clocked on the rising edge of the clock.
Multi-purpose input or Channel B Transmit external clock
input. The transmit data is clocked on the falling edge of the
clock.
Multi-purpose input or Channel B receive external clock input.
The transmit data is clocked on the rising edge of the clock.
Chip select (active low). A low at this pin enables the serial
port / CPU data transfer operation.
Bi-directional data bus. Eight bit, three state data bus to
transfer information to or from the CPU. D0 is the least
significant bit of the data bus and the first serial data bit to be
received or transmitted.
Write strobe (active low). A low on this pin will transfer the
contents of the CPU data bus to the addressed register.
Read strobe (active low). A low on this pin will transfer the
contents of the XR88C92/192 register to CPU data bus.
Power supply input, 2.97V to 5.5V.
No Connection.
6
Pin Description