XR16L2751CM EXAR [Exar Corporation], XR16L2751CM Datasheet - Page 36

• Manufacturer Part Number: XR16L2751CM
• Description: 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
• Manufacturer: EXAR [Exar Corporation]

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This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
User Programmable Transmit/Receive Trigger Level Register.
TRG[7:0]: Trigger Level Register
These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects
between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1).
This register is accessible when LCR = 0xBF. Note that this register is not identical to the FIFO Level Count
Register which is located in the general register set when FCTR bit-6 = 1 (Scratchpad Register Swap). It is
suggested to read the FIFO Level Count Register at the Scratchpad Register location when FCTR bit-6 = 1.
See
FC[7:0]: RX/TX FIFO Level Count
Receive/Transmit FIFO Level Count. Number of characters in Receiver FIFO (FCTR[7] = 0) or Transmitter FIFO
(FCTR[7] = 1) can be read via this register.
This register controls the XR16L2751 new functions.
FCTR[1:0]: RTS Hysteresis
User selectable RTS# hysteresis levels for hardware flow control application. After reset, these bits are set to
“0”. See
FCTR[2]: IrDa RX Inversion
FCTR[3]: Auto RS-485 Direction Control
The 2751 has hardware pin 37 to enable this auto RS-485 direction control function from power up, however,
pin 37 must be tied to VCC for this bit to gain control else auto RS-485 is always active.
FCTR[5:4]: Transmit/Receive Trigger Table Select
See
4.16
4.17
4.18
4.19
Logic 0 = Select RX input as encoded IrDa data (Idle state will be logic 0).
Logic 1 = Select RX input as inverted encoded IrDa data (Idle state will be logic 1).
Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
becomes empty and transmit shift register is shifting data out.
Logic 1 = Enable Auto RS485 Direction Control function. The direction control signal, RTS# pin, changes its
output logic state from low to high one bit time after the last stop bit of the last character is shifted out. Also,
the Transmit interrupt generation is delayed until the transmitter shift register becomes empty. The RTS#
output pin will automatically return to a logic low when a data byte is loaded into the TX FIFO. However,
RTS# behavior can be inverted by setting EMSR[3] = 1.
Table
Table
Device Revision Register (DREV) - Read Only
Trigger Level (TRG) - Write-Only
FIFO Data Count Register (FC) - Read-Only
Table 14
Feature Control Register (FCTR) - Read/Write
13.
11.
for more details.
FCTR
B
IT
0
0
1
1
-5
T
ABLE
FCTR
B
IT
0
1
0
1
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
-4
15: T
Table-A (TX/RX)
Table-B (TX/RX)
Table-C (TX/RX)
Table-D (TX/RX)
RIGGER
36
T
ABLE
T
ABLE
S
ELECT
XR16L2751
REV. 1.0.0