XR16L78464-TQFP EXAR [Exar Corporation], XR16L78464-TQFP Datasheet - Page 26

• Manufacturer Part Number: XR16L78464-TQFP
• Description: HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
• Manufacturer: EXAR [Exar Corporation]

XR16L784
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
T
A
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
0 0 1 0
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 0
A3-A0
ABLE
DDRESS
12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION.
TXCNT
TXTRG
FCTR
N
MCR
RHR
DLM
MSR
MSR
THR
FCR
LCR
SPR
EFR
R
DLL
LSR
IER
ISR
AME
EG
R
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EAD
W
W
W
W
RITE
R
R
R
R
/
RX FIFO
RX FIFO
DSR# Int.
Enable
Enable
Enable
Trigger
Divisor
E
RS485
Enable
FIFOs
Pres-
DLY-3
B
Table
CTS/
BRG
caler
TRG
Bit-7
Bit-7
Bit-7
Bit-7
CTS/
Bit-7
Auto
DSR
Bit-7
Bit-7
RROR
Bit-1
CD
IT
0
0
-7
RX FIFO
DTR# Int.
Enable
Trigger
Set TX
Enable
RS485
Enable
Enable
FIFOs
Empty
Break
DLY-2
B
Table
RTS/
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
TRG
DTR
Bit-6
Bit-6
RTS/
TSR
Auto
Bit-0
IR
RI
IT
0
0
-6
TX FIFO
Xon/Xoff/
Sp. Char.
Set Par-
XonAny
Special
Enable
Trigger
RS485
RS485
Empty
Enable
Delta-
Select
DLY-1
B
Char
Bit-5
Bit-5
Bit-5
Bit-5
Flow
THR
DSR
Bit-5
Auto
Bit-5
Bit-5
Cntl
Int.
ity
IT
0
0
0
-5
26
Xoff/spe-
TX FIFO
RX Input
cial char
Lopback
Invert IR
Internal
FCR[5:4],
MCR[7:5]
IER [7:4],
ISR [5:4],
MSR[7:4]
Trigger
Enable
RS485
Break
Parity
DLY-0
B
Enable
Even
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
CTS
RX
IT
0
0
-4
Hyst Bit-
Framing
Modem
Enable
Source
Enable
Status
Parity
Mode
OP2
B
Delta
DMA
Error
RTS/
Soft-
ware
Flow
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
CD#
Bit-3
DTR
Bit-3
Bit-3
Bit-3
Cntl
INT
Int.
RX
IT
0
3
-3
2
Stop Bits
TX FIFO
Flow Sel
Hyst Bit-
RX Line
RX Par-
ity Error
Source
Enable
Status
Reset
B
OP1
Delta
RTS/
RTS/
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
DTR
Bit-2
DTR
Soft-
ware
Flow
Bit-2
Bit-2
Bit-2
Cntl
INT
RI#
Int.
IT
0
2
-2
2
S
HADED BITS ARE ENABLED BY
RX FIFO
Pin Con-
Hyst Bit-
Overrun
Enable
Source
Length
Empty
DSR#
Reset
RTS#
B
Word
Delta
RTS/
Soft-
ware
Flow
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
DTR
Bit-1
Bit-1
Bit-1
Cntl
INT
TX
Int.
trol
RX
IT
0
1
-1
Pin Con-
RX Data
RX Data
Hyst Bit-
Source
Enable
Enable
Length
Ready
FIFOs
áç
áç
áç
áç
DTR#
CTS#
B
Word
Delta
RTS/
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
DTR
Soft-
ware
Flow
Bit-0
Bit-0
Bit-0
Cntl
INT
Int.
trol
IT
0
0
-0
REV. 1.2.0
User Data
C
LCR[7]=0
LCR[7]=1
LCR[7]=1
LCR[7]=0
EFR B
OMMENT
IT
-4.