XR20V2172IL64 EXAR [Exar Corporation], XR20V2172IL64 Datasheet - Page 22

• Manufacturer Part Number: XR20V2172IL64
• Description: TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
• Manufacturer: EXAR [Exar Corporation]

A
0x01
0x02
0x02
0x03
0x05
0x07
0x06
0x07
0x08
0x09
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
.
0x00
0x00
0x04
0x06
DDR
TXLVL
RXLVL
T
N
RHR
MCR
MSR
THR
FCR
SPR
TCR
R
LCR
LSR
TLR
IER
ISR
ABLE
AME
EG
8: INTERNAL REGISTERS DESCRIPTION.
RD/WR
RD/WR Divisor
RD/WR
RD/WR
RD/WR Resume
RD/WR RX Trig
RD/WR
RD/WR
R
W
WR
WR
RD
RD
RD
RD
EAD
RITE
/
RX FIFO
RX FIFO
CTS Int.
Enabled
Enable
Trigger
Enable
FIFOs
Select
Global
Clock
Pres-
B
Error
Input
caler
Bit-7
Bit-7
CD#
Bit-7
Bit-3
Bit-3
IT
0/
0/
0
0
-7
RI# Input
RX FIFO
Resume
RTS Int.
Enabled
RX Trig
Trigger
Enable
Set TX
THR &
FIFOs
Empty
Break
B
Bit-6
Bit-6
Bit-6
Bit-2
Bit-2
Bit-6
Bit-6
TSR
IT
0/
0/
-6
16C550 Compatible Registers
TX FIFO
Set Par-
Resume
XonAny
Xoff Int.
RX Trig
Enable
Source
Trigger
Empty
DSR#
B
Input
Bit-5
Bit-5
Bit-5
THR
Bit-5
Bit-1
Bit-1
Bit-5
Bit-5
INT
IT
ity
0/
0/
0/
0/
PRELIMINARY
-5
Even Par-
RX Break
TX FIFO
Lopback
Resume
Internal
Enable
Source
Trigger
Enable
RX Trig
22
Sleep
CTS#
Mode
B
Input
Bit-4
Bit-4
Bit-4
Bit-4
Bit-0
Bit-0
Bit-4
Bit-4
INT
IT
ity
0/
0/
0/
-4
S
HADED BITS ARE ENABLED WHEN
INT Out-
Stat. Int.
Framing
Modem
TX Trig
Enable
Source
Enable
Enable
Enable
OP2#/
Mode
Parity
B
Delta
DMA
Error
Bit-3
Bit-3
Bit-3
CD#
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Halt
INT
put
RX
IT
-3
TX FIFO
and TLR
Stat. Int.
RX Line
TX Trig
Enable
Source
Enable
Reset
Parity
B
Delta
Error
Bit-2
Bit-2
Bit-2
Stop
TCR
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Halt
INT
Bits
RI#
RX
IT
0/
-2
Source
Control
TX Trig
Enable
Length
Output
Empty
Reset
DSR#
RTS#
Over-
B
Word
Delta
FIFO
Error
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Halt
INT
RX
RX
run
TX
Int
IT
-1
RX Data
RX Data
Control
Enable
Source
Enable
Length
Output
TX Trig
Ready
FIFOs
DTR#
CTS#
B
Word
Delta
EFR B
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Halt
INT
Int.
IT
-0
IT
See
See
See
See
-4=1
LCR ≠ 0xBF
REV. P1.0.1
C
LCR[7]=0
OMMENT
Table 12
Table 13
Table 12
Table 13