XR16M2752IJ44 EXAR [Exar Corporation], XR16M2752IJ44 Datasheet - Page 30
![no-image](/images/no-image-200.jpg)
XR16M2752IJ44
Manufacturer Part Number
XR16M2752IJ44
Description
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
Manufacturer
EXAR [Exar Corporation]
Datasheet
1.XR16M2752IJ44.pdf
(52 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR16M2752IJ44-F
Manufacturer:
Exar Corporation
Quantity:
10 000
XR16M2752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space", LOW state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
•
•
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL, DLM and DLD) enable.
•
•
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
•
•
MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by
EFR bit-6. The RTS# pin can also be used for Auto RS485 Half-Duplex direction control enabled by FCTR bit-
3. If the modem interface is not used, this output may be used as a general purpose output.
•
•
MCR[2]: Reserved
OP1# is not available as an output pin on the M2752. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
MCR[3]: OP2# Output
OP2# is available as an output pin on the M2752 when AFR[2:1] = ‘00’. In the Loopback Mode, MCR[3] is used
to write the state of the modem CD# interface signal. Also see pin descriptions for MF# pins.
•
•
MCR[4]: Internal Loopback Enable
•
•
MCR[5]: Xon-Any Enable (requires EFR bit-4 = 1)
•
•
4.7
Logic 0 = No TX break condition (default).
Logic 1 = Forces the transmitter output (TX) to a “space”, LOW, for alerting the remote receiver of a line
break condition.
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers are selected.
Logic 0 = Force DTR# output HIGH (default).
Logic 1 = Force DTR# output LOW.
Logic 0 = Force RTS# HIGH (default).
Logic 1 = Force RTS# LOW.
Logic 0 = Forces OP2# output HIGH (default).
Logic 1 = Forces OP2# output LOW.
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and
Logic 0 = Disable Xon-Any function (default).
Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and
the M2752 is programmed to use the Xon/Xoff flow control.
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
30
Figure
12.
REV. P1.0.0