XR16M670IB25 EXAR [Exar Corporation], XR16M670IB25 Datasheet
XR16M670IB25
Available stocks
Related parts for XR16M670IB25
XR16M670IB25 Summary of contents
Page 1
TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO SEPTEMBER 2008 GENERAL DESCRIPTION 1 The XR16M670 (M670 enhanced Universal Asynchronous Receiver and Transmitter (UART) with 32 bytes of transmit and receive FIFOs, selectable transmit and receive FIFO trigger ...
Page 2
... QFN Corner CTS# VCC ORDERING INFORMATION P N ART UMBER XR16M670IL24 XR16M670IL32 XR16M670IB25 24- QFN, 32- QFN 25-BGA P PIN PIN AND DSR CD# 26 IOR GND VCC IOW# ...
Page 3
REV. 1.0.0 PIN DESCRIPTIONS Pin Description 24-QFN 32-QFN 25-BGA N AME DATA BUS INTERFACE ...
Page 4
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO Pin Description 24-QFN 32-QFN 25-BGA N AME DSR CD RI ANCILLARY SIGNALS XTAL1 8 10 XTAL2 - ...
Page 5
REV. 1.0.0 1.0 PRODUCT DESCRIPTION The XR16M670 (M670 high performance single channel UART. The configuration registers set is 16550 UART compatible for control, status and data transfer. Additionally, the M670 channel has 32 bytes of transmit and receive ...
Page 6
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The ...
Page 7
REV. 1.0.0 2.2 Serial Interface The M670 is typically used with RS-232, RS-485 and IR transceivers. The following figure shows typical connections from the UART to the different transceivers. For more information on RS-232 and RS-485/422, check www.exar.com or contact ...
Page 8
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO F 5. XR16M670 T S IGURE YPICAL ERIAL DTR# UART NTERFACE ONNECTIONS VCC VCC RTS# DE VCC RE# NC CTS# ...
Page 9
REV. 1.0.0 2.3 Device Reset The RESET input resets the internal registers and the serial interface outputs to their default state (see Table 16). An active high pulse of longer than 40 ns duration will be required to activate the ...
Page 10
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO 2.6 Crystal Oscillator or External Clock Input The M670 includes an on-chip oscillator to produce a clock for the baud rate generators in the device when a crystal is connected ...
Page 11
REV. 1.0.0 2.7 Programmable Baud Rate Generator with Fractional Divisor The M670 has independent Baud Rate Generators (BRGs) with prescalers for the transmitter and receiver. The prescalers are controlled by a software bit in the MCR register. The MCR register ...
Page 12
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO IGURE AUD ATE ENERATOR Prescaler Divide by 1 Crystal XTAL1 Osc / XTAL2 Buffer Prescaler Divide ABLE YPICAL DATA RATES ...
Page 13
REV. 1.0.0 2.8 Transmitter The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 32 bytes of FIFO which includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X/4X internal clock. A ...
Page 14
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO 2.8.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with bytes of transmit data. The THR empty flag (LSR bit-5) is set whenever ...
Page 15
REV. 1.0 IGURE ECEIVER PERATION IN NON 16X Clock ( DLD[5:4] ) Receive Data Byte and Errors F 11 IGURE ECEIVER PERATION IN 16X lock ...
Page 16
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO 2.10 Auto RTS (Hardware) Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote ...
Page 17
REV. 1.0.0 transmission as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re-asserted (LOW), indicating more data may be sent. F 12. A RTS CTS F IGURE ...
Page 18
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO 2.13 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the ...
Page 19
REV. 1.0.0 interrupt and place the address byte in the RX FIFO. The software then examines the byte and enables the receiver if the address matches its slave address, otherwise, it does not enable the receiver. If the receiver has ...
Page 20
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO F 13 IGURE NFRARED RANSMIT ATA TX Data Transmit IR Pulse (TX Pin) Receive IR Pulse (RX pin) RX Data 2.17 Sleep Mode with Auto Wake-Up and ...
Page 21
REV. 1.0.0 an interrupt is pending from any channel. The M670 will stay in the sleep mode of operation until it is disabled by setting IER bit logic 0. A word of caution: owing to the starting up ...
Page 22
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO 2.18 Internal Loopback The M670 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All ...
Page 23
REV. 1.0.0 3.0 UART INTERNAL REGISTERS The complete register set for the M670 is shown in T ABLE DDRESSES DREV - Device Revision DVID - Device Identification Register 0 0 ...
Page 24
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO T 7: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit ...
Page 25
REV. 1.0 INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE DREV RD Bit DVID DLL RD/WR ...
Page 26
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO 4.3 Interrupt Enable Register (IER) - Read/Write The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. These interrupts are ...
Page 27
REV. 1.0.0 IER[3]: Modem Status Interrupt Enable • Logic 0 = Disable the modem status register interrupt (default). • Logic 1 = Enable the modem status register interrupt. IER[4]: Sleep Mode Enable (requires EFR[ • Logic 0 = ...
Page 28
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO 4.4.2 Interrupt Clearing: • LSR interrupt is cleared by a read to the LSR register. • RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level. ...
Page 29
REV. 1.0.0 4.5 FIFO Control Register (FCR) - Write-Only This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and enable the wake up interrupt. They are defined as follows: FCR[0]: TX and ...
Page 30
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO ABLE RANSMIT AND FCR B -7 FCR B -6 FCR ...
Page 31
REV. 1.0.0 LCR[4]: TX and RX Parity Select If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format. • Logic 0 = ODD Parity is generated by ...
Page 32
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO MCR[1]: RTS# Output The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by EFR bit-6. If the modem interface is ...
Page 33
REV. 1.0.0 4.8 Line Status Register (LSR) - Read Only This register provides the status of data transfers between the UART and the host. If IER bit-2 is enabled, LSR bit 1 will generate an interrupt immediately and LSR bits ...
Page 34
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO 4.9 Modem Status Register (MSR) - Read Only This register provides the current state of the modem interface input signals. Lower four bits of this register are used to indicate ...
Page 35
REV. 1.0.0 4.10 Modem Status Register (MSR) - Write Only This register provides the advanced features of XR16M670. Lower four bits of this register are reserved. Writing to the higher four bits enables additional functions. MSR[3:0]: Reserved MSR[4]: Enable/Disable Transmitter ...
Page 36
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO EMSR[2]: Send TX Immediately • Logic not send TX immediately (default). • Logic 1 = Send TX immediately. When FIFO is enabled and this bit is set, ...
Page 37
REV. 1.0.0 DLD[6]: Independent BRG enable • Logic 0 = The Transmitter and Receiver uses the same Baud Rate Generator. (default). • Logic 1 = The Transmitter and Receiver uses different Baud Rate Generators. Use DLD[7] for selecting which baud ...
Page 38
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO FCTR[6]: Scratchpad Swap • Logic 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode. • Logic 1 = FIFO Count register (Read-Only), Enhanced ...
Page 39
REV. 1.0.0 EFR[4]: Enhanced Function Bits Enable Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 3-5, MCR bits 5-7, and DLD to be modified. After modifying any enhanced bits, EFR bit-4 can be ...
Page 40
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO REGISTERS DLM, DLL (Both TX and RX) DLD RHR THR IER FCR ISR LCR MCR LSR MSR SPR EMSR FC FCTR EFR XON1 XON2 XOFF1 XOFF2 I/O SIGNALS TX RTS# ...
Page 41
REV. 1.0.0 ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (32-QFN) Thermal Resistance (24-QFN) Thermal Resistance (25-BGA) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS ...
Page 42
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO SEE”POWER-SAVE FEATURE” ON PAGE 21. M670 should NOT be lower than its VCC supply. AC ELECTRICAL CHARACTERISTICS - ...
Page 43
REV. 1.0.0 AC ELECTRICAL CHARACTERISTICS - YMBOL ARAMETER T Delay From Center of Start To Reset SRT TXRDY# T Reset Pulse Width RST Bclk Baud Clock ...
Page 44
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO F 17 IGURE ODE NTEL ATA A0-A2 Valid Address T AS CS# IOR# T RDV D0- IGURE ODE ...
Page 45
REV. 1.0 & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR & I IGURE RANSMIT EADY NTERRUPT TX Start D0:D7 (Unloading) Bit IER[1] ...
Page 46
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO F 21 & I IGURE ECEIVE EADY NTERRUPT Start Bit RX S D0:D7 S D0:D7 Stop Bit INT T SSR RXRDY# First Byte is Received in RX FIFO ...
Page 47
REV. 1.0.0 PACKAGE DIMENSIONS (24 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO ) ...
Page 48
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO PACKAGE DIMENSIONS (32 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL ...
Page 49
REV. 1.0.0 PACKAGE DIMENSIONS (25 PIN BGA - 0.8 Seating Plane Note: The control dimension is the millimeter column SYMBOL 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO ...
Page 50
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO REVISION HISTORY D R ATE EVISION September 2008 Rev 1.0.0 Final Datasheet. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to ...
Page 51
REV. 1.0.0 GENERAL DESCRIPTION................................................................................................ 1 F .................................................................................................................................................... 1 EATURES A .............................................................................................................................................. 1 PPLICATIONS F 1. XR16M670 B D IGURE LOCK IAGRAM IGURE IN UT SSIGNMENT OR ............................................................................................................................... 2 ORDERING INFORMATION PIN DESCRIPTIONS ........................................................................................................ 3 ...
Page 52
XR16M670 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO 4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 27 4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 27 4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. ABLE NTERRUPT OURCE AND RIORITY 4.5 ...