71M6534 MAXIM [Maxim Integrated Products], 71M6534 Datasheet - Page 90

• Manufacturer Part Number: 71M6534
• Description: Exceeds IEC 62053/ANSI C12.20 Standards
• Manufacturer: MAXIM [Maxim Integrated Products]

71M6533/G/H and 71M6534/H Data Sheet
90
LCD_Y
M26MHZ
M40MHZ
MPU_DIV[2:0]
MUX_ALT
MUX_DIV[3:0]
MUX_SYNC_E
OPT_FDC[1:0]
2021[6]
2005[4]
2005[0]
2004[2:0]
2005[2]
209D[3:0]
2020[7]
2007[1:0]
0
0
0
0
0
0
0
0
L
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LCD Blink Frequency (ignored if blink is disabled or if the segment is off).
M26MHZ and M40MHZ set the master clock (MCK) frequency. These bits are reset on
chip reset and may only be set. Attempts to write zeroes to M40MHZ and M26MHZ are
ignored.
The MPU clock divider (from MCK). These bits may be programmed by MPU without
risk of losing control.
The MPU asserts this bit when it wishes the MUX to perform ADC conversions on an
alternate set of inputs.
If CHOP_E is 00, MUX_ALT is automatically asserted once per sum cycle, when
XFER_BUSY falls.
The number of states in the input multiplexer.
When set, SEG7 outputs MUX_SYNC. Otherwise, SEG7 is an LCD pin.
Selects the modulation duty cycle for OPT_TX.
MPU_DIV[2:0]
OPT_FDC[1:0]
M40MHZ
0 =
1 =
0
0
1
1
000
001
010
011
100
101
110
111
00
01
10
11
1 Hz (500 ms ON, 500 ms OFF)
0.5 Hz (1 s ON, 1 s OFF)
M26MHZ
0
1
0
1
Resulting Clock Frequency
MCK/4
MCK/8
MCK/16
MCK/32
MCK/64
MCK/128
MCK/265
MCK/265
Function
50% Low
25% Low
12.5% Low
6.25% Low
MCK Frequency
26.7 MHz
20 MHz
40 MHz
40 MHz
FDS_6533_6534_004
Rev 2