XRP7740ILB-AAAA-F EXAR [Exar Corporation], XRP7740ILB-AAAA-F Datasheet - Page 20

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XRP7740ILB-AAAA-F

Manufacturer Part Number
XRP7740ILB-AAAA-F
Description
Quad-Output Digital PWM Buck Controller Supporting high current loads
Manufacturer
EXAR [Exar Corporation]
Datasheet
XRP7740
Quad-Output Digital PWM Buck Controller
REV 1.1.0
Over-Current Fault Handling
When an over-current condition occurs, PWM drivers in the corresponding channels are disabled. After a 200ms
timeout, the controller is re-powered and soft-start is initiated. When the over-current condition is reached the
controller will check the SET_FAULT_RESP_CONFIG_LB and SET_FAULT_RESP_CONFIG_HB to determine
whether there are any “following” channels that need to be similarly restarted. The controller will also set the fault
flags in READ_OVC_FAULT_WARN register.
Typically the over-current fault threshold would be set to 130-140% of the maximum desirable output current. This
will help avoid any over-current conditions caused by transients that would shut down the output channel.
Chip Operation and Configuration
Soft-Start
The SET_SS_RISE_CHx register is a 16 bit register which specifies the soft-start delay and the ramp
characteristics for a specific channel. This register allows the customer to program the channel with a 250us step
resolution and up to a maximum 16ms delay.
Bits [15:10] specify the delay after enabling a channel but before outputting pulses; where each bit represents
250us steps. Bits [9:0] specify the rise time of the channel; these 10 bits define the number of microseconds for
each 50mV increment to reach the target voltage.
Channel Power Up Sequence
EXAR RESERVES THE RIGHT TO MAKE CHANGES TO THIS DATASHEET.
EXAR CONFIDENTIAL, PRELIMINARY & PROPRIETARY. DO NOT DISTRIBUTE OR COPY.
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