NCN8025A ONSEMI [ON Semiconductor], NCN8025A Datasheet - Page 4

• Manufacturer Part Number: NCN8025A
• Description: Compact SMART CARD Interface IC
• Manufacturer: ONSEMI [ON Semiconductor]

NOTE:
PIN FUNCTION AND DESCRIPTION
(QFN24)
Pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
6
7
8
9
All information below refers to QFN−24 pin numbering unless otherwise noted. This information can be transposed to
the QFN−16 package according to the above “PIN FUNCTION AND DESCRIPTION” Table.
(QFN16)
Pin
10
12
13
14
15
16
17
11
−
−
−
5
6
7
8
−
9
−
−
−
CMDVCC
PORADJ
CLKDIV1
CLKDIV2
AUX1uc
AUX2uc
CAUX2
CAUX1
VSEL1
RSTIN
CLKIN
CRST
CVCC
Name
CCLK
I/Ouc
GND
VDD
GND
GND
INT
Ground
Ground
Ground
Output
Output
Output
Output
Output
Output
Output
Output
Output
Power
Power
Input /
Input /
Input /
Input/
Input/
Type
Input
Input
Input
input
Input
Input
Input
Input
This pin handles the connection to the chip card’s serial auxiliary AUX2 I/O pin (C8). A
bi−directional level translator adapts the serial I/O signal between the card and the micro
controller. A 11 kW (typical) pull up resistor to CVCC provides a High impedance state for
the smart card C8 pin.
This pin handles the connection to the chip card’s serial auxiliary AUX1 I/O pin (C4). A
bi−directional level translator adapts the serial I/O signal between the card and the micro
controller. A 11 kW (typical) pull up resistor to CVCC provides a High impedance state for
the smart card C4 pin.
Card Ground
This pin is connected to the CLOCK card connector’s pin (Chip card’s pin C3). The Clock
signal comes from the CLKIN input through clock dividers and level shifter.
This pin is connected to the chip card’s RESET pin (C2) through the card connector. A
level translator adapts the external Reset (RSTIN) signal to the smart card.
This pin is connected to the smart card power supply pin (C1). An internal low dropout
regulator is programmable using the pins VSEL0 and VSEL1 to supply either 5 V or 3 V
or 1.8 V output voltage. An external distributed ceramic capacitor ranging from 80 nF to
1.2 mF recommended must be connected across CVCC and CGND. This set of capacitor
(if distributed) must be low ESR (< 100 mW).
Command V
sequence is enabled by toggling CMDVCC High to Low and when a card is present.
Power−on reset threshold adjustment input pin for changing the reset threshold (V
UVLO threshold) thanks to an external resistor power divider. Needs to be connected to
ground when unused.
This Reset input connected to the host and referred to VDD (microcontroller side), is
connected to the smart card Reset pin through the internal level shifter which translates
the level according to the CVCC programmed value.
This pin is connected to the system controller power supply. It configures the level shifter
input stage to accept the signals coming from the controller. A 0.1 mF decoupling
capacitor shall be used. When V
Ground
The interrupt request is activated LOW on this pin. This is enabled when a card is present
and the card presence is detected by PRES or PRES pins. Similarly an interrupt is
generated when CVCC is overloaded. Inverter output (An open−drain output configuration
with 50 kW pull−up resistor is available under request (metal change)).
Clock Input for External Clock
This pin is connected to an external micro−controller. A bi−directional level translator
adapts the serial I/O signal between the smart card and the external controller. A built−in
constant 11 kW (typical) resistor provides a high impedance state.
This pin is connected to an external micro−controller. A bi−directional level translator
adapts the serial C4 signal between the smart card and the external controller. A built−in
constant 11 kW (typical) resistor provides a high impedance state.
This pin is connected to an external micro−controller. A bi−directional level translator
adapts the serial C8 signal between the smart card and the external controller. A built−in
constant 11 kW (typical) resistor provides a high impedance state.
This pin coupled with CLKDIV2 is used to program the clock frequency division ratio
(Table 2).
This pin coupled with CLKDIV1 is used to program the clock frequency division ratio
(Table 2).
Allows selecting card V
VSEL0 = Low: CVCC = 5 V when VSEL1 = High or 3 V when VSEL1 = Low.
VSEL0 = High: CVCC = 1.8 V when VSEL1 = High or 3 V when VSEL1 = Low.
Regulator Power Supply Ground
http://onsemi.com
CC
pin. Activation sequence Enable/Disable pin (active Low). The activation
4
CC
power supply voltage.
DD
is below 2.30 V typical the card pins are disabled.
Description
DD