WM8951L_07 WOLFSON [Wolfson Microelectronics plc], WM8951L_07 Datasheet - Page 23

• Manufacturer Part Number: WM8951L_07
• Description: Stereo ADC with Microphone Input and Clock Generator
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

Production Data
Figure 19 Right Justified Mode
Figure 20 DSP Mode
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DSP mode is where the left channel MSB is available on either the 1
(selectable by LRP) following a LRC transition high. Right channel data immediately follows left
channel data.
In all modes ADCLRC must always change on the falling edge of BCLK, refer to Figure 17, Figure
18, Figure 19 and Figure 20.
Operating the digital audio interface in DSP mode allows ease of use for supporting the various
sample rates and word lengths. The only requirement is that all data is transferred within the correct
number of BCLK cycles to suit the chosen word length.
In order for the digital audio interface to offer similar support in the three other modes (Left Justified,
I
more careful consideration.
In Slave mode, ADCLRC is not required to have a 50:50 mark-space ratio. BCLK input need not be
continuous. It is however required that there are sufficient BCLK cycles for each ADCLRC transition
to clock the chosen data word length. The non-50:50 requirement on the LRC is of use in some
situations such as with a USB 12MHZ clock. Here simply dividing down a 12MHz clock within the
DSP to generate LRC and BCLK will not generate the appropriate ADCLRC since it will no longer
change on the falling edge of BCLK. For example, with 12MHz/32k fs mode there are 375 MCLK per
LRC. In these situations ADCLRC can be made non 50:50.
In Master mode, ADCLRC will be output with a 50:50 mark-space ratio with BCLK output at 64 x
base frequency (i.e. 48 kHz).
2
S and Right Justified), the ADCLRC and BCLK frequencies, continuity and mark-space ratios need
st
PD Rev 4.1 December 2007
or 2
nd
rising edge of BCLK
WM8951
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