WM8951L_07 WOLFSON [Wolfson Microelectronics plc], WM8951L_07 Datasheet - Page 9
![no-image](/images/no-image-200.jpg)
WM8951L_07
Manufacturer Part Number
WM8951L_07
Description
Stereo ADC with Microphone Input and Clock Generator
Manufacturer
WOLFSON [Wolfson Microelectronics plc]
Datasheet
1.WM8951L_07.pdf
(42 pages)
- Current page: 9 of 42
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Production Data
MASTER CLOCK TIMING
Figure 1 System Clock Timing Requirements
Figure 2 Clock Out Timing Requirements
w
Test Conditions
AVDD1, AVDD2, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, T
256fs unless otherwise stated.
PARAMETER
System Clock Timing Information
XTI/MCLK System clock pulse
width high
XTI/MCLK System clock pulse
width low
XTI/MCLK System clock cycle time
XTI/MCLK Duty cycle
Test Conditions
AVDD1, AVDD2, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, T
256fs unless otherwise stated.
PARAMETER
System Clock Timing Information
CLKOUT propagation delay
from XTI/MCLK falling edge
XTI/MCLK
CLKOUT
CLKOUT
XTI/MCLK
(DIV X2)
SYMBOL
t
COP
SYMBOL
t
t
t
XTIH
XTIL
XTIY
t
XTIL
t
XTIY
TEST CONDITIONS
t
COP
t
TEST CONDITIONS
XTIH
A
A
= +25
= +25
40:60
MIN
MIN
18
18
54
o
o
0
C, Slave Mode fs = 48kHz, XTI/MCLK =
C, Slave Mode fs = 48kHz, XTI/MCLK =
TYP
TYP
PD Rev 4.1 December 2007
60:40
MAX
MAX
10
WM8951
UNIT
UNIT
ns
ns
ns
ns
9
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