ISPPAC-CLK5510V LATTICE [Lattice Semiconductor], ISPPAC-CLK5510V Datasheet - Page 19

• Manufacturer Part Number: ISPPAC-CLK5510V
• Description: In-System Programmable Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
One important point to note is that the termination supplies must have low impedance and be able to both source
and sink current without experiencing fluctuations. These requirements generally preclude the use of a resistive
divider network, which has an impedance comparable to the resistors used, or of commodity-type linear voltage
regulators, which can only source current. The best way to develop the necessary termination voltages is with a
regulator specifically designed for this purpose. Because SSTL and HSTL logic is commonly used for high-perfor-
mance memory busses, a suitable termination voltage supply is often already available in the system.
Figure 14. SSTL2, SSTL3, HSTL Receiver Configuration
Differential HSTL and SSTL
HSTL and SSTL are sometimes used in a differential form, especially for distributing clocks in high-speed memory
systems. Figure 15 shows how ispClock5500 reference input should be configured for accepting these standards.
The major difference between the differential and single-ended forms of these logic standards is that in the differen-
tial cases, the REFA- input is used as a signal input, not a reference level, and that both terminating resistors are
engaged and set to 50Ω.
Figure 15. Differential HSTL/SSTL Receiver Configuration
VTT
VTT
+Signal In
-Signal In
Signal In
REFVTT
VREF IN
REFVTT
REFA+
REFA-
REFA+
REFA-
ispClock5500
ispClock5500
50
50
CLOSED
CLOSED
50
19
CLOSED
OPEN
Differential
Differential
Receiver
Receiver
ispClock5500 Family Data Sheet