ISPPAC-CLK5510V LATTICE [Lattice Semiconductor], ISPPAC-CLK5510V Datasheet - Page 37

• Manufacturer Part Number: ISPPAC-CLK5510V
• Description: In-System Programmable Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Detailed Pin Descriptions
VCCO_[0..9], GNDO_[0..9] – These pins provide power and ground for each of the output banks. In the case when
an output bank is unused, its corresponding VCCO pin may be left unconnected or preferably should be tied to
ground. ALL GNDO pins should be tied to ground regardless of whether the associated bank is used or not. When
a bank is used, it should be individually bypassed with a capacitor in the range of 0.01 to 0.1uF as close to its
VCCO and GNDO pins as is practical.
BANK_[0..9]A, BANK_[0..9]B – These pins provide clock output signals. The choice of output divider (V0-V4) and
output driver type (CMOS, LVDS, SSTL, etc.) may be selected on a bank-by-bank basis. When the outputs are con-
figured as pairs of single-ended outputs, output impedance and slew rate may be selected on an output-by-output
basis.
Pin Descriptions (Continued)
VCCD
GNDD
VCCJ
REFA+
REFA-
REFB+
REFB-
REFSEL
REFVTT
TDO
TDI
TCK
TMS
LOCK
SGATE
GOE
OEX
OEY
PS0
PS1
PLL_BYPASS PLL Bypass
RESET
TEST1
TEST2
n/c
Reserved
1. Internal pull-down resistor.
2. Internal pull-up resistor.
Pin Name
Digital Core VCC
Digital GND
JTAG interface VCC
Clock Reference A positive input
Clock Reference A negative input
Clock Reference B positive input
Clock Reference B negative input
Clock Reference Select input (LVCMOS)
Termination voltage for reference inputs
JTAG TDO Output line
JTAG TDI Input line
JTAG Clock Input
JTAG Mode Select
PLL Lock indicator, LOW indicates PLL lock
Synchronous output gate
Global Output Enable
Output Enable 1
Output Enable 2
Profile Select 0
Profile Select 1
Reset PLL
Test Input 1 - connect to GNDD
Test Input 2 - connect to GNDD
No internal connection
Factory use only - Do not connect
Description
37
Pin Type
Output
Output
Power
Power
Power
Input
Input
Input
Input
Input
Input
Input
Input
GND
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
n/a
n/a
1
2
2
1
1
1
1
1
15, 16, 17, 23, 48
ispClock5500 Family Data Sheet
ispClock5510
48 TQFP
24, 33
36
18
19
—
—
—
20
35
39
38
37
34
40
42
21
22
44
43
47
41
46
45
—
—
Pin Number
1, 2, 23, 24, 25, 26, 27,
32, 33, 34, 35, 36, 37,
28, 29, 48, 49, 50, 75,
76, 77, 78, 79, 94, 97,
ispClock5520
80, 81, 95, 96
98, 99, 100
100 TQFP
47, 71
46, 93
74
38
39
42
41
43
40
73
84
83
82
72
85
87
44
45
89
88
92
86
91
90