ISPPAC-CLK5510V LATTICE [Lattice Semiconductor], ISPPAC-CLK5510V Datasheet - Page 27

• Manufacturer Part Number: ISPPAC-CLK5510V
• Description: In-System Programmable Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Figure 23. Additional Factor-of-2 Division in Coarse Mode
When one moves from fine skew mode to coarse skew mode with a given divider configuration, the VCO frequency
will attempt to double to compensate for the additional divide-by-2 stage. Because the f
however, one must modify the V-divider settings to bring f
640MHz). This can be accomplished by dividing all V-divider settings by two. All output frequencies will remain
unchanged from what they were in fine mode. One drawback of moving from fine skew mode into coarse skew
mode is that it may not be possible to maintain consistent output frequencies, as only those V-divider settings which
are multiples of four (in fine mode) may be divided by two. For example, a V-divider setting of 24 will divide down to
12, which is also a legal V-divider setting, whereas an initial setting of 26 would divide down to 13, which is not a
valid setting.
When one moves from coarse skew mode to fine skew mode, the extra divide-by-two factor is removed from
between the VCO and the V-divider bank, halving the VCO’s effective operating frequency. To compensate for this
change, all of the V-dividers must be doubled to move the VCO back into its specified operating range and maintain
consistent output frequencies. The only situation in which this may be a problem is when a V-divider initially in
coarse mode has a value greater than 32, as the corresponding fine skew mode setting would be greater than 64,
which is not supported.
Skew Matching and Accuracy
Understanding the various factors which relate to output skew is essential for realizing optimal skew performance in
the ispClock5500 family of devices.
In the case where two outputs are identically configured, and driving identical loads, the maximum skew is defined
by t
error between two matched outputs.
Figure 24. Skew Matching Error Sources
SKEW,
which is specified as a maximum of 50ps. In Figure 24 the Bank1A and BANK2A outputs show the skew
(skew setting = 0)
(skew setting = 2ns)
(skew setting=0)
VCO
BANK1A
BANK2A
BANK3A
+/- t
SKEW
÷2
27
2ns +/- (t
Mode
Coarse
Fine
VCO
Mode
back into its specified operating range (320MHz to
SKEW
) +/- (t
V-dividers
ispClock5500 Family Data Sheet
SKERR
)
VCO
Fout
range is not increased,