AGL015V2-CS144 ACTEL [Actel Corporation], AGL015V2-CS144 Datasheet - Page 112

• Manufacturer Part Number: AGL015V2-CS144
• Description: IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
• Manufacturer: ACTEL [Actel Corporation]

IGLOO DC and Switching Characteristics
Clock Conditioning Circuits
Table 2-169 • IGLOO CCC/PLL Specification
2 -9 8
Parameter
Clock Conditioning Circuitry Input Frequency f
Clock Conditioning Circuitry Output Frequency f
Delay Increments in Programmable Delay Blocks
Number of Programmable Values in Each Programmable Delay Block
Serial Clock (SCLK) for Dynamic PLL
Input Cycle-to-Cycle Jitter (peak magnitude)
CCC Output Peak-to-Peak Period Jitter F
Acquisition Time
Tracking Jitter
Output Duty Cycle
Delay Range in Block: Programmable Delay 1
Delay Range in Block: Programmable Delay 2
Delay Range in Block: Fixed Delay
Notes:
1. This delay is a function of voltage and temperature. See
2. T
3. Maximum value obtained for a Std. speed grade device in Worst-Case Commercial Conditions. For specific
4. For the definitions of Type 1 and Type 2, refer to the PLL Block Diagram in the
5. The AGL030 device does not support PLL.
6. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL
for deratings.
junction temperature and voltage supply levels, refer to
in IGLOO and ProASIC3 Devices
input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by
the period jitter parameter.
0.75 MHz to 24 MHz
24 MHz to 100 MHz
100 MHz to 250 MHz
J
= 25°C, V
CCC Electrical Specifications
Timing Characteristics
For IGLOO V2 or V5 Devices, 1.5 V DC Core Supply Voltage
CC
= 1.5 V
1, 2, 4
3
chapter of the handbook.
CCC_OUT
1, 2, 4
1, 2, 4
IN_CCC
OUT_CCC
A d v a n c e v 0. 5
1, 2
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
Table 2-6 on page 2-6
Table 2-6 on page 2-6
Network
1 Global
Maximum Peak-to-Peak Period Jitter
0.50%
1.00%
2.50%
0.025
Used
Min.
0.75
1.25
48.5
1.5
for derating values.
External
FB Used
Clock Conditioning Circuits
0.75%
1.50%
3.75%
and
Typ.
360
3.5
Table 2-7 on page 2-7
Networks
3 Global
0.70%
1.20%
2.75%
15.65
15.65
Max.
Used
250
250
100
300
51.5
6.0
2.5
1.5
32
1
Units
MHz
MHz
ms
ns
ns
ns
ns
ps
ns
ns
µs
%
ns