LFEC LATTICE [Lattice Semiconductor], LFEC Datasheet - Page 13

• Manufacturer Part Number: LFEC
• Description: LatticeECP/EC Family Data Sheet
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
adjustment and not relock until the t
allows the user to adjust the phase and duty cycle of the CLKOS output.
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated
with it: input clock divider, feedback divider, post scalar divider and secondary clock divider. The input clock divider
is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. The post
scalar divider allows the VCO to operate at higher frequencies than the clock output, thereby increasing the fre-
quency range. The secondary divider is used to derive lower frequency outputs.
Figure 2-11. PLL Diagram
Figure 2-12 shows the available macros for the PLL. Table 2-5 provides signal description of the PLL Block.
Figure 2-12. PLL Primitive
CLKFB
(from CLKOP,
clock net or
external pin)
(from routing or
external pin)
CLKI
RST
CLKFB
CLKI
Input Clock
Divider
(CLKI)
EPLLB
Feedback
(CLKFB)
Divider
LOCK
Dynamic Delay Adjustment
CLKOP
LOCK
parameter has been satisfied. Additionally, the phase and duty cycle block
Adjust
Delay
DDAIDEL[2:0]
DDA MODE
Controlled
DDAILAG
Oscillator
2-10
Voltage
DDAIZR
VCO
CLKFB
CLKI
RST
Post Scalar
(CLKOP)
Divider
EHXPLLB
LatticeECP/EC Family Data Sheet
Phase/Duty
Secondary
(CLKOK)
Divider
CLKOP
CLKOS
CLKOK
LOCK
DDAOZR
DDAOLAG
DDAODEL[2:0]
Select
Clock
Architecture
LOCK
CLKOS
CLKOP
CLKOK