LFEC LATTICE [Lattice Semiconductor], LFEC Datasheet - Page 59

• Manufacturer Part Number: LFEC
• Description: LatticeECP/EC Family Data Sheet
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
LatticeECP/EC sysCONFIG Port Timing Specifications
sysCONFIG Byte Data Flow
t
t
t
t
t
t
t
t
t
sysCONFIG Byte Slave Clocking
t
t
t
sysCONFIG Serial (Bit) Data Flow
t
t
t
t
t
sysCONFIG Serial Slave Clocking
t
t
sysCONFIG POR, Initialization and Wake Up
t
t
t
t
t
t
t
t
t
t
sysCONFIG SPI Port
t
t
t
t
t
t
f
Parameter
SUCBDI
HCBDI
CODO
SUCS
HCS
SUWD
HWD
DCB
CORD
BSCH
BSCL
BSCYC
SUSCDI
HSCDI
CODO
SUMCDI
HMCDI
SSCH
SSCL
ICFG
VMC
PRGMRJ
PRGM
DINIT
DPPINIT
DPPDONE
IODISS
IOENSS
MWC
CFGX
CSSPI
CSCCLK
SOCDO
SOE
CSPID
MAXSPI
Byte D[0:7] Setup Time to CCLK
Byte D[0:7] Hold Time to CCLK
Clock to Dout in Flowthrough Mode
CS[0:1] Setup Time to CCLK
CS[0:1] Hold Time to CCLK
Write Signal Setup Time to CCLK
Write Signal Hold Time to CCLK
CCLK to BUSY Delay Time
Clock to out for read Data
Byte Slave Clock Minimum High Pulse
Byte Slave Clock Minimum Low Pulse
Byte Slave Clock Cycle Time
Din Setup Time to CCLK Slave Mode
Din Hold Time to CCLK Slave Mode
Clock to Dout in Flowthrough Mode
Din Setup Time to CCLK Master Mode
Din Hold Time to CCLK Master Mode
Serial Slave Clock Minimum High Pulse
Serial Slave Clock Minimum Low Pulse
Minimum Vcc to INIT High
Time from t
PROGRAMB Pin Pulse Rejection
PROGRAMB Low Time to Start Configuration
PROGRAMB High to INIT High Delay
Delay Time from PROGRAMB Low to INIT Low
Delay Time from PROGRAMB Low to DONE Low
User I/O Disable from PROGRAMB Low
User I/O Enabled Time from CCLK Edge During Wake-up Sequence
Additional Wake Master Clock Signals after Done Pin High
Init High to CCLK Low
Init High to CSSPIN Low
CCLK Low before CSSPIN Low
CCLK Low to Output Valid
CSSPIN Active Setup Time
CSSPIN Low to First Clock Edge Setup Time
Max Frequency for SPI
ICFG
to valid Master Clock
Over Recommended Operating Conditions
Description
3-23
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
300+3cyc
Min
120
300
15
25
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7
1
7
1
7
1
6
6
7
1
7
1
6
6
0
600+6cyc
Max
TBD
12
12
10
37
25
15
—
—
—
—
—
—
12
—
—
—
—
—
—
—
—
—
50
—
37
25
—
—
20
2
1
1
2
-
cycles
Units
MHz
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
µs
us
ns
ns
ns
ns