A54SX16-1CG256 ACTEL [Actel Corporation], A54SX16-1CG256 Datasheet - Page 23

• Manufacturer Part Number: A54SX16-1CG256
• Description: SX Family FPGAs RadTolerant and HiRel
• Manufacturer: ACTEL [Actel Corporation]

Figure 1-17 • Register Cell Timing Characteristics – Flip-Flops
Timing Characteristics
Timing characteristics for SX devices fall into three
categories: family-dependent, device-dependent, and
design-dependent.
characteristics are common to all SX family members.
Internal routing delays are device-dependent. Design
dependence means actual delays are not determined
until after placement and routing of the user’s design is
complete. Delay values may then be determined by using
the Timer tool or performing simulation with post-layout
delays.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most time-
critical paths. Critical nets are determined by net
property assignment prior to placement and routing. Up
to 6 percent of the nets in a design may be designated as
critical, whereas 90 percent of the nets in a design are
typical.
PRESET
CLK
CLR
The
Q
D
input
t
SUD
and
output
CLK
(Positive Edge Triggered)
D
buffer
t
t
HPWH'
RPWH
PRESET
CLR
v2.1
t
HD
t
RCO
Long Tracks
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows,
columns, or modules. Long tracks employ three and
sometimes five antifuse connections. This increases
capacitance and resistance, resulting in longer net delays
for macros connected to long tracks. Typically up to 6
percent of nets in a fully utilized device require long
tracks. Long tracks contribute approximately 4 ns to 8.4
ns delay. This additional delay is represented statistically
in higher fanout (FO = 24) routing delays in the data
sheet specifications section.
Timing Derating
SX devices are manufactured in a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process variations. Minimum
timing parameters reflect maximum operating voltage,
minimum
processing.
minimum
temperature, and worst-case processing.
Q
t
t
HPWL'
RPWL
t
WASYN
t
CLR
operating
operating
Maximum
SX Family FPGAs RadTolerant and HiRel
t
HP
t
PRESET
voltage,
temperature,
timing
maximum
parameters
and
operating
best-case
reflect
1-19