HT1382_1105 HOLTEK [Holtek Semiconductor Inc], HT1382_1105 Datasheet - Page 17

• Manufacturer Part Number: HT1382_1105
• Description: I2C/3-Wire Real Time Clock
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

HT1382
I
Rev. 1.40
2
C/3-Wire Real Time Clock
Acknowledge
Device Addressing
Write Operation
Each bytes of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level placed
on the bus by the receiver. The master generates an extra acknowledge related clock pulse. A slave
receiver which is addressed must generate an acknowledge (ACK) after the reception of each byte.
The acknowledging device must first pull down the SDA line during the acknowledge clock pulse so
that it remains LOW during the HIGH period of this clock pulse. A master receiver must signal an end
of data to the slave by generating a not-acknowledge (NACK) bit on the last byte that has been clocked
out of the slave. In this case, the master receiver must leave the data line HIGH during the 9th pulse to
not acknowledge. The master will generate a STOP or repeated START condition.
The slave address byte is the first byte received following the START condition from the master
device. The first seven bits of the first byte make up the slave address. The eighth bit defines a read or
write operation to be performed. When this R/W bit is 1 , then a read operation is selected. A 0
selects a write operation. The device address bits are 1101000 . When an address byte is sent, the
device compares the first seven bits after the START condition. If they match, the device outputs an
acknowledge on the SDA line.
Byte Write Operation
A byte write operation requires a START condition, a slave address with R/ bit, a valid Register
Address, the required Data and a STOP condition. After each of the three byte transfers, the device
responds with an ACK.
Page Write Operation
Following a START condition and slave address, a R/ bit is placed on the bus which indicates to the
addressed device that a Register Address will follow which is to be written to the address pointer.
The data to be written to the memory follows next and the internal address pointer is incremented to
the next address location on the reception of an acknowledge clock. After reaching memory location
0Fh, the pointer will be reset to 00h.
Data Output
By Transmitter
Data Output
By Receiver
SCL from
Master
S
1 1 0 1 0 0 0 0
Slave Address
condition
START
Write
S
MSB
The first byte after the START.
1
ACK
Byte Write Sequence
1
1
Register Address(An)
0
1
2
17
0
0
0
ACK
R/W
not acknowledge
LSB
7
acknowledge
Data(n)
8
acknowledgement
clk pulse for
ACK
9
P
May 27, 2011