HT82A520R HOLTEK [Holtek Semiconductor Inc], HT82A520R Datasheet

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... Up to 0.33 s instruction cycle with 12MHz system clock at V =5V DD General Description The HT82A520R/HT82A620R are 8-bit high perfor- mance RISC-like microcontrollers designed for USB keyboard mouse and joystick product applications. The advantages of low power consumption, I/O flexibil- ity, programmable frequency divider, timer functions, ...

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... Block Diagram HT82A520R HT82A620R Rev.1.00 HT82A520R/HT82A620R 2 October 23, 2009 ...

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... Pin Assignment Rev.1.00 HT82A520R/HT82A620R 3 October 23, 2009 ...

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... D+/CLK I/O V33O O VSS Rev.1.00 HT82A520R/HT82A620R Description Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is output or Schmitt Trigger input. When if output, Configuration op- tion may choose CMOS or NMOS. Configuration options determine if the pins have pull-high resistors ...

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... Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev.1.00 HT82A520R/HT82A620R Description Bi-directional 8-bit input/output port. Each bit can be configured as wake-up input by option (bit option). Software instructions determine if the pin is output or Schmitt Trigger input ...

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... Pull-high Resistance for DATA PH1 R Pull-high Resistance for CLK PH2 Additional Power Consumption I * ADC if A/D Converter is Used DNL* A/D Differential Non-Linearity INL* A/D Integral Non-Linearity RESOLU* Resolution Note: for HT82A620R Rev.1.00 HT82A520R/HT82A620R Test Conditions Min. V Conditions DD f =6MHz 2.2 SYS f =12MHz 4.0 SYS No load, f =6MHz, SYS 5V ...

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... A/D Clock Period A/D Conversion Time ADC t * A/D Sample Time ADCS t SPI SCS to SCK Time CS_SK t SPI Clock Time SPICK Note: t =1/f SYS SYS for HT82A620R Rev.1.00 HT82A520R/HT82A620R Test Conditions Min. V Conditions DD 2.2V~5.5V 4.0V~5.5V f =6MHz 0 SYS f =12MHz 0 SYS 5V 1 Wake-up from HALT 400 ...

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... The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one Rev.1.00 HT82A520R/HT82A620R instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cy- cles, the pipelining structure of the microcontroller en- sures that instructions are effectively executed in one instruction cycle ...

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... Note: PC11~PC8: Current Program Counter bits #11~#0: Instruction code address bits Rev.1.00 HT82A520R/HT82A620R After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the ac- knowledge signal will be inhibited ...

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... SIZA, SDZA, CALL, RET, RETI Program Memory The Program Memory is the location where the user code or program is stored. The HT82A520R/ HT82A620R is a One-Time Programmable, OTP, mem- ory type device where users can program their applica- tion code into the device. By using the appropriate ...

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... Instruction b11 b10 b9 TABRDC [m] PC11 PC10 PC9 TABRDL [ Note: PC11~PC8: Current Program Counter bits @7~@0: Table Pointer TBLP bits Rev.1.00 HT82A520R/HT82A620R Table Location Bits PC8 @ Table Location TBHP register bit3~bit0 when TBHP is enabled ...

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... SET [m].i and CLR [m].i with the exception of a few dedicated bits. The Data Memory can also be accessed through the memory pointer register MP. Rev.1.00 HT82A520R/HT82A620R microcontrollers, such as ACC, PCL, etc., have the same Data Memory address. General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later ...

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... The important point to note here is that in the example shown above, no reference is made to specific Data Memory ad- dresses. Rev.1.00 HT82A520R/HT82A620R physically exist as normal registers. The method of indi- rect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified ...

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... Note that the lower order table data byte is transferred to a user de- fined location. Rev.1.00 HT82A520R/HT82A620R Status Register - STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). ...

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... All I/O ports have a designated register correspondingly labeled as PA, PB, PC. These labeled Rev.1.00 HT82A520R/HT82A620R I/O registers are mapped to specific addresses within the Data Memory as shown in the Data Memory table, which are used to transfer the appropriate output or in- put data on that port ...

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... Rev.1.00 HT82A520R/HT82A620R Port B VDDIO Function The output drivers of most I/O pins use the VDD power supply line as their high voltage level. In this device pins PB0~PB6 can use a different voltage, other than VDD as their high level ...

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... One of these is a high to low transition of any of the port pins. Single or multiple pins on the ports can be setup to have this function. Read/Write Timing Rev.1.00 HT82A520R/HT82A620R Timer/Event Counters The provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. This device contains a single count-up timer of 16-bit capacity ...

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... At the same time the data in the low byte Timer/Event Counter Control Register Rev.1.00 HT82A520R/HT82A620R buffer will be transferred into its associated low byte timer register. For this reason, the low byte timer regis- ter should be written first when preloading data into the 16-bit timer registers ...

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... The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the Interrupt Control Register, INTC0, is reset to zero. Rev.1.00 HT82A520R/HT82A620R Configuring the Event Counter Mode In this mode, a number of externally changing logic events, occurring on the external timer pin, can be re- corded by the Timer/Event Counter. To operate in this ...

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... Not Pulse Width Measure Mode Timing Chart Rev.1.00 HT82A520R/HT82A620R until the enable bit is again set high by the program can the timer begin further pulse width measurements. In this way, single shot pulse measurements can be easily made ...

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... Timer/Event Counter _ note mode bits must be previously setup Rev.1.00 HT82A520R/HT82A620R register will be set. If the timer interrupt is enabled this will in turn generate an interrupt signal. However irre- spective of whether the timer interrupt is enabled or not, a Timer/Event counter overflow will also generate a wake-up signal if the device Power-down condi- tion ...

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... When this happens, the Program Counter, which stores the address of the next instruction Rev.1.00 HT82A520R/HT82A620R to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new ad- dress which will be the value of the corresponding inter- rupt vector ...

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... Rev.1.00 HT82A520R/HT82A620R INTC0 Register INTC1 Register 23 October 23, 2009 ...

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... TF, will be automatically re- set and the EMI bit will be automatically cleared to dis- able other interrupts. Rev.1.00 HT82A520R/HT82A620R SPI Interrupt For a SPI Interrupt to occur, the global interrupt enable bit, EMI, and the corresponding SPI interrupt enable bit, ESII must be first set. An actual SPI Interrupt will take ...

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... I/O port and port control registers will power high condition ensuring that all pins will be first set to inputs. Rev.1.00 HT82A520R/HT82A620R Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing a proper reset operation ...

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... Watchdog time-out flag TO will be set WDT Time-out Reset during Normal Operation Timing Chart Rev.1.00 HT82A520R/HT82A620R Watchdog Time-out Reset during Power Down The Watchdog time-out Reset during Power Down is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Pro- gram Counter and the Stack Pointer will be cleared to 0 and the TO flag will be set to 1 ...

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... UINT 0000 1111 0000 uuuu TBHP xxxx xxxx uuuu uuuu USC 1000 0000 uuuu xuux USR 0000 0000 uuuu uuuu Rev.1.00 HT82A520R/HT82A620R RES Reset WDT RES Reset (Normal Time-out (HALT) Operation) (HALT)* xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx ...

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... SBDR xxxx xxxx uuuu uuuu SPIR ---- 0000 ---- 0000 Note: * means warm reset , - not implemented u means unchanged , x means unknown ** for HT82A620R Rev.1.00 HT82A520R/HT82A620R RES Reset WDT RES Reset (Normal Time-out (HALT) Operation) (HALT)* 0000 0000 0000 0000 uuuu uuuu 0000 0000 ...

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... A crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator. No other external components are required. The HT82A520R/HT82A620R can operate with 6MHz or 12MHz system clocks. In order to make sure that the USBSIE functions properly, the user should correctly configure the SYSCLK bit of the UCC Register ...

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... HALT instruction, this will be executed immediately after the 1024 system clock period delay has ended. Rev.1.00 HT82A520R/HT82A620R Watchdog Timer The Watchdog Timer is provided to prevent program mal- functions or sequences from jumping to unknown loca- tions, due to certain uncontrollable external events such as electrical noise ...

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... PWM2DRL~ 3 8+4 PB0 PWM2DRH Rev.1.00 HT82A520R/HT82A620R PWM Registers Three register, located in the Data Memory are assigned to each Pulse Width Modulator output and are known as the PWM registers each register pair that the 12-bit value, which represents the overall duty cycle of one modulation cycle of the output waveform, should be placed ...

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... PWM0 output disabled Rev.1.00 HT82A520R/HT82A620R PWM Output Control The three outputs, PWM0, PWM1, and PWM2 are shared with pins PA4, PA5 and PB0. To operate as a PWM output and not as an I/O pin, bit 0 of the relevant PWM low byte register bit must be set high. A zero must ...

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... Bit R/W 7~0 R/W PWM Base Period Register PWMBR0 ~ PWMBR2 Rev.1.00 HT82A520R/HT82A620R 8+4 PWM Mode PWM Register Pairs Description Used to define the base period of the PWM Range =1 ~ 256 (1/f or 4/f chosen via the PWM_S bit) SYS SYS where PWMBRn=0~255 (n= 0~2) 33 October 23, 2009 ...

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... D6 Note: D11~D0 is the A/D conversion result data bit MSB~LSB. A/D Data Register Rev.1.00 HT82A520R/HT82A620R A/D Converter Control Register - ADCR To control the function and operation of the A/D con- verter, control registers known as ADCR and ADSR are provided. These 8-bit registers define functions such as the selection of which analog channel is connected to ...

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... I/O pins. If the 4-bit address on PCR3~PCR0 has a value of A/D Converter Clock Source Register Rev.1.00 HT82A520R/HT82A620R A/D Converter Control Register 1111 or higher, then all 16 pins, namely AN0~ AN15 will all be set as analog inputs. Note that if the PCR3~PCR0 ...

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... A/D converter after the channel selection bits have changed, then, within a time frame of one to ten instruc- tion cycles, the START bit in the ADCR register must Rev.1.00 HT82A520R/HT82A620R first be set high and then immediately cleared to zero. This will ensure that the EOCB flag is correctly set to a high condition. ...

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... Rev.1.00 HT82A520R/HT82A620R pulsing the START bit in the ADCR register immediately after the channel selection bits have changed state. The exception to this is where the channel selection bits are all cleared, in which case the A/D converter is not required to be re-initialised ...

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... SBDR register is used for data storage. The SPIR register is used to select SPI mode, clock polar- ity edge selection and SPI enable or disable selection. Rev.1.00 HT82A520R/HT82A620R Ideal A/D Transfer Function After Power on, the contents of the SBDR register will unknown condition while the SBCR register will de- ...

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... TRF data transmitted or received, 0= data is transmitting or still not received CPOL: I/O = clock polarity rising/falling edge: For SPIR Register. If clock polarity set to rising edge (SPI_CPOL=1), serial clock timing follow SCK, otherwise (SPI_CPOL=0) SCK is the serial clock timing. Rev.1.00 HT82A520R/HT82A620R Function SPIR Register SPI Block Diagram 39 ...

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... TXRX buffer until all the data has been received at which point it will be latched into the SBDR register. Rev.1.00 HT82A520R/HT82A620R Step 6. Check the WCOL bit, if set high then a collision error has occurred so return to step5. If equal to zero then go to the following step. ...

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... The bit will be set high by the Serial Inter- face but has to be cleared by the user application pro- gram. The overall function of the WCOL bit can be disabled or enabled by a configuration option. Rev.1.00 HT82A520R/HT82A620R SPI Share Function Pins Status CSEN SCS SCK ...

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... Rev.1.00 HT82A520R/HT82A620R SPI Bus Timing 42 October 23, 2009 ...

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... Rev.1.00 HT82A520R/HT82A620R SPI Transfer Control Flowchart 43 October 23, 2009 ...

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... VDDIO, in which case power will be sup- plied on pin PB7. In the latter configuration, PB7 will be configured as a power pin VDDIO and not a normal I/O pin. For the MCU VDD, it supplies all the HT82A520R/ HT82A620R circuit except the USB SIE which is supply by UBUS. USB Suspend Wake-Up Remote Wake-Up If there is no signal on the USB bus for over 3ms, the de- vice will enter a suspend mode ...

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... Controls the USB endpoint1 interrupt. Default value EP1EN R/W 1: enabled 0: disabled Controls the USB endpoint2 interrupt. Default value EP2EN R/W 1: enabled 0: disabled Controls the USB endpoint3 interrupt. Default value EP3EN R/W 1: enabled 0: disabled 4~7 Unused bit, read as 0 Rev.1.00 HT82A520R/HT82A620R Function USB_STAT Register Function UINT1 Register 45 October 23, 2009 ...

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... When this bit is set to 1 (set by SIE), it indicates that endpoint 3 has been ac- 3 EP3F R/W cessed and a USB interrupt will occur. When the interrupt has been serviced, this bit should be cleared by software. Default value Default value 4~7 Unused bit, read as 0 Rev.1.00 HT82A520R/HT82A620R Function USC Register Function USR Register 46 October 23, 2009 ...

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... Set by the users when related USB endpoints were stalled. Cleared by a USB reset. STL0~ 0~3 R/W STL3 The STL0 is also cleared by a Setup Token event. Default value is 0000 . 4~7 Unused bit, read as 0 Rev.1.00 HT82A520R/HT82A620R Function UCC Register Function AWR Register Function STALL Register 47 resistor between D+ and ...

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... Firmware. Default value READY R To show that the desired FIFO is ready. To show that the host sent a 0-sized packet to the MCU. This bit must be cleared LEN0 R read action to the corresponding FIFO. Rev.1.00 HT82A520R/HT82A620R Function SIES Register Function MISC Register 48 October 23, 2009 ...

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... Define endpoint 2 FIFO size E2FS1, E2FS0: 4 E2FS0 00: 8-byte (default) R/W 5 E2FS1 01: 16-byte 10: 32-byte 11: 64-byte Define endpoint 3 FIFO size E3FS1, E3FS0: 6 E3FS0 00: 8-byte (default) R/W 7 E3FS1 01: 16-byte 10: 32-byte 11: 64-byte UFC0 USB FIFO Size Control Register 0 Rev.1.00 HT82A520R/HT82A620R Function Function Function 49 October 23, 2009 ...

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... CLR WDT instructions: one or two clear WDT instruction( NMOS or CMOS output type 14 PA wake-up enable/disable by bit 16 PB7 mode: GPIO or V DDIO 17 VDD PB0~PB6: PB0~PB6 power source from V 18 SPI_WCOL: enable/disable Rev.1.00 HT82A520R/HT82A620R Function Options pin for PB0~PB6 power source DDIO 50 October 23, 2009 ...

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... RES high. X1 can use 6MHz or 12MHz close OSC1 & OSC2 as possible. * These capacitors should be placed close to the USB connector. ** This capacitor should be placed close to the MCU.. Rev.1.00 HT82A520R/HT82A620R 51 October 23, 2009 ...

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... Within the Holtek microcontroller instruction set are a range of add and Rev.1.00 HT82A520R/HT82A620R subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to en- sure correct handling of carry and borrow data when re- sults exceed 255 for addition and less than 0 for subtraction ...

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... DECA [m] Decrement Data Memory with result in ACC DEC [m] Decrement Data Memory Rev.1.00 HT82A520R/HT82A620R Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT in- struction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electro- magnetic environments ...

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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev.1.00 HT82A520R/HT82A620R Description 54 Cycles Flag Affected ...

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... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev.1.00 HT82A520R/HT82A620R 55 October 23, 2009 ...

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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev.1.00 HT82A520R/HT82A620R addr 56 October 23, 2009 ...

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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev.1.00 HT82A520R/HT82A620R October 23, 2009 ...

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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev.1.00 HT82A520R/HT82A620R addr 58 October 23, 2009 ...

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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev.1.00 HT82A520R/HT82A620R Stack Stack Stack [m]. 0~6) 59 October 23, 2009 ...

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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev.1.00 HT82A520R/HT82A620R [m]. 0~6) 60 October 23, 2009 ...

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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev.1.00 HT82A520R/HT82A620R [ October 23, 2009 ...

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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev.1.00 HT82A520R/HT82A620R 0 [m] [ October 23, 2009 ...

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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev.1.00 HT82A520R/HT82A620R [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 63 October 23, 2009 ...

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... The result is stored in the Data Memory. Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev.1.00 HT82A520R/HT82A620R 64 October 23, 2009 ...

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... Package Information 20-pin SSOP (150mil) Outline Dimensions Symbol Symbol Rev.1.00 HT82A520R/HT82A620R Dimensions in inch Min. Nom. 0.228 0.150 0.008 0.335 0.049 0.025 0.004 0.015 0.007 0 Dimensions in mm Min. Nom. 5.79 3.81 0.20 8.51 1.24 0.64 0.10 0.38 0. Max. 0.244 0.158 0.012 ...

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... SSOP (150mil) Outline Dimensions Symbol Symbol Rev.1.00 HT82A520R/HT82A620R Dimensions in inch Min. Nom. 0.228 0.150 0.008 0.335 0.054 0.025 0.004 0.022 0.007 0 Dimensions in mm Min. Nom. 5.79 3.81 0.20 8.51 1.37 0.64 0.10 0.56 0. Max. 0.244 0.157 0.012 0.346 0.060 ...

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... SSOP (150mil) Outline Dimensions Symbol Symbol Rev.1.00 HT82A520R/HT82A620R Dimensions in inch Min. Nom. 0.228 0.150 0.008 0.386 0.054 0.025 0.004 0.022 0.007 0 Dimensions in mm Min. Nom. 5.79 3.81 0.20 9.80 1.37 0.64 0.10 0.56 0. Max. 0.244 0.157 0.012 0.394 0.060 ...

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... SAW Type 32-pin (5mm´5mm) QFN Outline Dimensions Symbol Symbol Rev.1.00 HT82A520R/HT82A620R Dimensions in inch Min. Nom. 0.028 0.000 0.008 0.007 0.197 0.197 0.020 0.049 0.049 0.012 Dimensions in mm Min. Nom. 0.70 0.00 0.20 0.18 5.00 5.00 0.50 1.25 1.25 0.30 68 Max. ...

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... Product Tape and Reel Specifications Reel Dimensions SSOP 20S (150mil), SSOP 24S (150mil), SSOP 28S (150mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev.1.00 HT82A520R/HT82A620R Dimensions in mm 330.0 1.0 100.0 1.5 +0.5/-0.2 13.0 2.0 0.5 +0.3/-0.2 16.8 22.2 0.2 69 October 23, 2009 ...

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... Description W Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev.1.00 HT82A520R/HT82A620R Dimensions in mm +0.3/-0.1 16.0 8.0 0.1 1.75 0.10 7.5 0.1 +0.1/-0.0 1.5 +0.25/-0.00 1.50 4.0 0.1 2.0 0.1 6.5 0.1 9.0 0.1 2.3 0.1 0.30 0.05 13.3 0.1 70 October 23, 2009 ...

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... Description W Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev.1.00 HT82A520R/HT82A620R Dimensions in mm +0.3/-0.1 16.0 8.0 0.1 1.75 0.10 7.5 0.1 +0.1/-0.0 1.5 +0.25/-0.00 1.50 4.0 0.1 2.0 0.1 6.5 0.1 9.5 0.1 2.1 0.1 0.30 0.05 13.3 0.1 Dimensions in mm 16.0 0.3 8.0 0.1 1.75 0.1 7.5 0.1 +0.10/-0.00 1.55 +0.25/-0.00 1.50 4.0 0.1 2 ...

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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev.1.00 HT82A520R/HT82A620R 72 October 23, 2009 ...