ISPLSI1032E-80LJ LATTICE [Lattice Semiconductor], ISPLSI1032E-80LJ Datasheet - Page 9

• Manufacturer Part Number: ISPLSI1032E-80LJ
• Description: High-Density Programmable Logic
• Manufacturer: LATTICE [Lattice Semiconductor]

1. Internal Timing Parameters are not tested and are for reference only.
Internal Timing Parameters
PARAM.
Outputs
t
t
t
t
t
Clocks
t
t
t
t
t
Global Reset
t
ob
sl
oen
odis
goe
gy0
gy1/2
gcp
ioy2/3
iocp
gr
49 Output Buffer Delay
50 Output Buffer Delay, Slew Limited Adder
51 I/O Cell OE to Output Enabled
52 I/O Cell OE to Output Disabled
53 Global OE
54 Clk Delay, Y0 to Global GLB Clk Line (Ref. clk)
55 Clk Delay, Y1 or Y2 to Global GLB Clk Line
56 Clk Delay, Clock GLB to Global GLB Clk Line
57 Clk Delay, Y2 or Y3 to I/O Cell Global Clk Line
58 Clk Delay, Clk GLB to I/O Cell Global Clk Line
59 Global Reset to GLB and I/O Registers
#
1
DESCRIPTION
Specifications ispLSI and pLSI 1032E
9
MIN.
1.4
1.4
0.8
0.0
0.8
–
–
–
–
–
–
-125
MAX.
1.4
1.4
1.8
0.0
1.8
1.3
9.9
4.3
4.3
2.7
2.8
MIN.
1.5
1.5
0.8
0.0
0.8
–
–
–
–
–
–
-100
MAX.
Table 2-0037A/1032E
10.0
1.5
1.5
1.8
0.0
1.8
2.0
5.1
5.1
3.9
4.3
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns