HT82V46 HOLTEK [Holtek Semiconductor Inc], HT82V46 Datasheet - Page 9

• Manufacturer Part Number: HT82V46
• Description: 16-Bit, 45MSPS, 3-Channel CCD/CIS Analog Signal Processor
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

Note: 1. The relationship between input video and sampling is controlled by CDS2 and CDS1.
Rev. 1.10
OD[7:0]
OD[7:0]
Analog
Analog
(R, G)
ADCK
CDS1
CDS2
ADCK
CDS1
CDS2
2. When CDS2 is high the input video signal is connected to the Video level sampling capacitors.
3. When CDS1 is high the analog input video signal is connected to the Reference level sampling capacitors.
4. CDS1 must not go high before the first falling edge of ADCK after CDS2 goes low.
5. It is required that the falling edge of CDS2 should occur before the rising edge of ADCK.
6. In 1-channel CDS mode it is not possible to have a equally spaced Video and Reference sample points
7. Non-CDS operation is also possible; CDS1 is not required in this mode.
Input
Input
(R)
with a 45MHz ADCK.
HB : High Byte; LB : Low Byte
n-5
HB : High Byte; LB : Low Byte
HB
G
t ADH
t ADH
HB
R
LB
G
Pixel n
t ADFC1R
n-8
HB
R
Pixel n
t ADFC1R
t ADL
LB
R
t
C1FC2R
LB
t
R
Figure 3 2-channel CDS Analog Input Timing
Figure 4 1-channel CDS Analog Input Timing
C1FC2R
t ADFC2R
n-4
t ADL
HB
G
t C2FADR
HB
R
LB
G
Pixel n+1
t ADC
n-7
t C1
HB
R
Pixel n+1
LB
9
R
t C1
LB
R
n-3
t C2
t C2
t C2FADR
HB
G
HB
R
LB
G
Pixel n+2
n-6
HB
R
Pixel n+2
t OD
t
t PR2
LB
OD
R
ADFC2R
LB
R
t
t PR1
n-2
ADFC2F
HB
G
HB
R
November 24, 2011
LB
G
Pixel n+3
t
OD
n-5
HT82V46
HB
Pixel n+3
R
t
OD
n-1
LB
R