ISPLSI3256A-50LM LATTICE [Lattice Semiconductor], ISPLSI3256A-50LM Datasheet - Page 6

• Manufacturer Part Number: ISPLSI3256A-50LM
• Description: In-System Programmable High Density PLD
• Manufacturer: LATTICE [Lattice Semiconductor]

1. Unless noted otherwise, all parameters use 20 PTXOR path and ORP.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
5. Reference Switching Test Conditions section.
PARAMETER
t
t
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
External Switching Characteristics
pd1
pd2
max
max (Ext.)
max (Tog.)
su1
co1
h1
su2
co2
h2
r1
rw1
ptoeen
ptoedis
goeen
goedis
toeen
toedis
wh
wl
su3
h3
COND.
TEST
C
C
C
A
A
A
–
–
–
A
–
–
–
–
A
–
B
B
B
–
–
–
–
5
10 GLB Reg. Clk to Output Delay
11 GLB Reg. Hold Time after Clk
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
18 Test OE Output Enable
19 Test OE Output Disable
20 Ext. Synchronous Clk Pulse Duration, High
21 Ext. Synchronous Clk Pulse Duration, Low
22 I/O Reg Setup Time before Ext. Sync Clk (Y3, Y4)
23 I/O Reg Hold Time after Ext. Sync Clk (Y3, Y4)
#
1 Data Prop. Delay, 4PT Bypass, ORP Bypass
2 Data Prop. Delay
3 Clk Frequency with Internal Feedback
4 Clk Frequency with Ext. Feedback
5 Clk Frequency, Max. Toggle
6 GLB Reg. Setup Time before Clk, 4 PT Bypass
7 GLB Reg. Clk to Output Delay, ORP Bypass
8 GLB Reg. Hold Time after Clk, 4 PT Bypass
9 GLB Reg. Setup Time before Clk
2
Over Recommended Operating Conditions
DESCRIPTION
1, 2, 3
4
1
6
(
3
tsu2 + tco1
Specifications ispLSI 3256A
1
)
MIN. MAX.
90.0
61.0
125
8.0
0.0
9.0
0.0
6.5
4.0
4.0
5.0
0.0
–
–
–
–
–
–
–
–
–
–
–
-90
12.0
15.0
13.5
16.0
16.0
10.0
10.0
10.0
10.0
7.5
9.0
–
–
–
–
–
–
–
–
–
–
–
–
MIN.
77.0
50.0
83.0
11.0
10.0
9.5
0.0
0.0
6.0
6.0
5.0
0.0
–
–
–
–
–
–
–
–
–
–
–
-70
MAX.
15.0
18.0
10.5
15.0
18.0
18.0
11.0
11.0
17.0
17.0
9.0
–
–
–
–
–
–
–
–
–
–
–
–
MIN.
57.0
37.0
63.0
12.5
15.0
13.5
0.0
0.0
8.0
8.0
7.0
0.0
–
–
–
–
–
–
–
–
–
–
–
-50
Table 2-0030C/3256A
MAX.
20.0
24.5
12.0
14.0
20.0
24.5
24.5
13.5
13.5
23.0
23.0
–
–
–
–
–
–
–
–
–
–
–
–
UNITS
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns