ISPLSI3256A-50LM LATTICE [Lattice Semiconductor], ISPLSI3256A-50LM Datasheet - Page 9

• Manufacturer Part Number: ISPLSI3256A-50LM
• Description: In-System Programmable High Density PLD
• Manufacturer: LATTICE [Lattice Semiconductor]

Derivations of
Note: Calculations are based on timing specs for the ispLSI 3256A-90L.
GOE0,1
Y0,1,2
ispLSI 3256A Timing Model
I/O Pin
Reset
(Input)
TOE
Y3,4
t
t
t
su
h
co
#52
15.4 ns
4.6 ns
3.7 ns
#51
I/O Reg Bypass
D
RST
Register
Input
#24
=
=
=
=
=
=
=
=
=
=
=
=
#25 - 29
t
I/O Cell
su,
Logic + Reg su - Clock (min)
(
(#24+ #30+ #34) + (#37) - (#24+ #30+ #43)
(1.9 + 2.4 + 6.4) + (1.0) - (1.9 + 2.4 + 2.8)
Clock (max) + Reg h - Logic
(
(#24+ #30+ #43) + (#38) - (#24+ #30+ #34)
(1.9 + 2.4 + 5.3) + (4.8) - (1.9 + 2.4 + 6.4)
Clock (max) + Reg co + Output
(
(#24 + #30 + #43) + (#39) + (#44 + #46)
(1.9 + 2.4 + 5.3) + (1.6) + (2.3 + 1.9)
t
t
t
iobp +
iobp +
iobp +
Q
t
h and
t
t
t
grp +
grp +
grp +
t
co from the Product Term Clock
t
t
t
20ptxor) + (
ptck(max)) + (
ptck(max)) + (
#30
GRP
GRP
#50
#53
#54
t
gsu) - (
t
t
gh) - (
gco) + (
t
4 PT Bypass
XOR Delays
#41 - 43
iobp +
Control
PTs
Feedback
t
iobp +
#33 - 35
20 PT
t
#32
#52
orp +
t
RE
OE
CK
9
grp +
t
grp +
t
Table 2-0042/3256A
ob)
GLB
#31
Specifications ispLSI 3256A
t
ptck(min))
t
1
20ptxor)
GLB Reg Bypass
D
RST
GLB Reg
Delay
#36
#37 - 40
Q
0902/3256A
ORP Bypass
Delay
ORP
ORP
#45
#44
#46, 47
I/O Cell
#48, 49
(Output)
I/O Pin