ISPLSI3256A-50LM LATTICE [Lattice Semiconductor], ISPLSI3256A-50LM Datasheet - Page 7

• Manufacturer Part Number: ISPLSI3256A-50LM
• Description: In-System Programmable High Density PLD
• Manufacturer: LATTICE [Lattice Semiconductor]

1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Internal Timing Parameters
PARAMETER
Inputs
t
t
t
t
t
t
GRP
t
GLB
t
t
t
t
t
t
t
t
t
t
t
t
t
ORP
t
t
iobp
iolat
iosu
ioh
ioco
ior
grp
4ptbp
4ptbp
1ptxor
20ptxor
xoradj
gbp
gsu
gh
gco
gro
ptre
ptoe
ptck
orp
orpbp
24 I/O Register Bypass
25 I/O Latch Delay
26 I/O Register Setup Time before Clock
27 I/O Register Hold Time after Clock
28 I/O Register Clock to Out Delay
29 I/O Register Reset to Out Delay
30 GRP Delay
31 4 Product Term Bypass Path Delay (Comb.)
32 4 Product Term Bypass Path Delay (Reg.)
33 1 Product Term/XOR Path Delay
34 20 Product Term/XOR Path Delay
35 XOR Adjacent Path Delay
36 GLB Register Bypass Delay
37 GLB Register Setup Time before Clock
38 GLB Register Hold Time after Clock
39 GLB Register Clock to Output Delay
40 GLB Register Reset to Output Delay
41 GLB Product Term Reset to Register Delay
42 GLB Product Term Output Enable to I/O Cell Delay
43 GLB Product Term Clock Delay
44 ORP Delay
45 ORP Bypass Delay
#
2
Over Recommended Operating Conditions
1
DESCRIPTION
3
7
Specifications ispLSI 3256A
MIN. MAX.
-3.7
5.7
1.0
4.8
2.8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
-90
10.9
1.9
4.2
2.8
2.4
4.8
4.8
5.4
6.4
6.9
0.1
1.6
2.6
8.6
4.9
5.3
2.3
0.9
–
–
–
–
MIN.
-5.2
6.2
1.8
6.0
3.2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
-70
MAX.
12.4
10.5
2.4
4.2
3.6
3.0
5.9
5.9
6.4
7.4
8.1
0.1
1.8
2.8
5.4
6.3
2.7
1.2
–
–
–
–
MIN.
-7.0
8.6
2.4
8.2
4.3
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
-50
Table 2-0036C/3256A
MAX.
15.8
10.1
11.1
14.2
3.3
5.3
4.9
4.1
7.6
7.6
8.8
0.1
2.2
3.8
7.3
8.5
3.6
1.6
–
–
–
–
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns