ISPLSI5128VE LATTICE [Lattice Semiconductor], ISPLSI5128VE Datasheet
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ISPLSI5128VE
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ISPLSI5128VE Summary of contents
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Features • Second Generation SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC DEVICE — 3.3V Power Supply — User Selectable 3.3V/2.5V I/O — 6000 PLD Gates / 128 Macrocells — 96 I/O Pins Available — 128 Registers — High-Speed Global Interconnect — ...
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Functional Block Diagram Figure 1. ispLSI 5128VE Functional Block Diagram (96-I/O) VCCIO 1 TOE I/O 1 I/O 2 I/O 3 I/O 20 I/O 21 I/O 22 I/O 23 RESET 1. CLK2, CLK3 and TOE signals are shared with I/O signals. ...
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Description (Continued) The 32 registered macrocells in the GLB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each macrocell contains a programmable XOR gate, a pro- grammable register/latch and the necessary clocks and ...
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Figure 2. ispLSI 5128VE Block Diagram (96 I/O) 24 CLK2 24 32 I/O CLK3 160 160 I 160 160 Specifications ispLSI 5128VE GLB2 ...
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Figure 3. ispLSI 5000VE Generic Logic Block (GLB) From GRP ...
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Figure 4. ispLSI 5000VE Macrocell PTOE GOE0 GOE1 TOE PT Clock PT Reset Shared PT Reset PT Preset speed/ power Note: Not all macrocells have I/O pads. Specifications ispLSI 5128VE Global PTOE 0 Global PTOE 1 Global PTOE 2 Global ...
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Global Clock Distribution The ispLSI 5000VE Family has four dedicated clock input pins: CLK0 - CLK3. CLK0 input is used as the dedicated master clock that has the lowest internal clock skew with no clock inversion to maintain the fastest ...
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Figure 6. Boundary Scan Register Circuit for I/O Pins SCANIN BSCAN (from previous Registers cell Shift DR Clock DR Figure 7. Boundary Scan Register Circuit for Input-Only Pins Input Pin SCANIN ...
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Figure 8. Boundary Scan Waveforms and Timing Specifications TMS TDI T btch TCK TDO Data to be captured Data to be driven out SYMBOL PARAMETER t btcp TCK [BSCAN test] clock pulse width t btch TCK [BSCAN test] pulse width ...
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Absolute Maximum Ratings Supply Voltage V .................................. -0.5 to +5.4V cc Input Voltage Applied ............................... -0.5 to +5.6V Tri-Stated Output Voltage Applied ........... -0.5 to +5.6V Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Ouput Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (See Figure 9) 3.3V TEST CONDITION R1 ...
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DC Electrical Characteristics for 2.5V Range SYMBOL PARAMETER V I/O Reference Voltage CCIO V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH 1. I/O voltage configuration must be set ...
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External Switching Characteristics ...
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External Switching Characteristics ...
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Internal Timing Parameters PARAMETER DESCRIPTION In/Out Delays t in Input Buffer Delay t gclk_in Global Clock Buffer Input Delay (clk0) t rst Global Reset Pin Delay t goe Global OE Pin Delay t buf Output Buffer Delay t en Output ...
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Timing Parameters (continued) BASE PARAMETER ADDER TYPE Routing Adders route Tioi Input Adders t clk1 gclk_in t clk2 gclk_in t clk3 gclk_in 1 Tioo Output Adders t t Slow Slew I/O buf ...
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Timing Model From Feedback t ROUTE t BLA INREG t GCLK_IN CLK t IOI t RST RST t OE GOE In/Out Delays Note: Italicized parameters are delay adders above and beyond default ...
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Power Consumption Power consumption in the ispLSI 5128VE device de- pends on two primary factors: the speed at which the device is operating and the number of product terms used. The product terms have a fuse-selectable speed/ power tradeoff setting. ...
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Signal Descriptions Signal Name TMS Input - This pin is the Test Mode Select input, which is used to control the JTAG state machine. TCK Input - This pin is the Test Clock input pin used to clock through the ...
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Pin Configuration ispLSI 5128VE 128-Pin TQFP (0.4mm Lead Pitch / 14.0mm x 14.0mm Body Size GND 7 I VCC 9 ...
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Part Number Description ispLSI 5128VE Device Family Device Number Speed f 180 = 180 MHz max f 125 = 125 MHz max f 100 = 100 MHz max MHz max Ordering Information FAMILY fmax (MHz) tpd ...