ISPLSI5128VE LATTICE [Lattice Semiconductor], ISPLSI5128VE Datasheet - Page 16

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ISPLSI5128VE

Manufacturer Part Number
ISPLSI5128VE
Description
In-System Programmable 3.3V SuperWIDE High Density PLD
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet

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1
Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for
details.
Routing Adders
Tioi Input Adders
Tioo Output Adders
Tbla Additional Block Loading Adders
ispLSI 5128VE Timing Parameters (continued)
LVCMOS25_out
LVCMOS33_out
Timing for open drain configurations is the same as non-open drain configurations.
ADDER TYPE
Slow Slew I/O
LVTTL_out
clk1
clk2
clk3
t
1
2
3
lp
BASE PARAMETER
1
t
t
t
buf,
buf,
buf,
t
t
t
t
buf,
t
t
t
t
gclk_in
gclk_in
gclk_in
route
route
route
route
t
t
t
en,
en,
en,
t
en
t
t
t
dis
dis
dis
-180
1.0
0.9
1.4
1.4
4.0
0.0
0.5
0.0
0.1
0.2
0.3
16
Specifications ispLSI 5128VE
-125
1.5
1.7
1.7
1.7
4.0
0.0
0.5
0.0
0.1
0.2
0.3
ADDER
-100
1.5
1.7
1.7
1.7
4.0
0.0
0.5
0.0
0.1
0.2
0.3
-80
1.5
1.7
1.7
1.7
4.0
0.0
0.5
0.0
0.1
0.2
0.3
Timing Table/5128VE
Timing v.2.0
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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