M52D16161A-10BG ESMT [Elite Semiconductor Memory Technology Inc.], M52D16161A-10BG Datasheet

Page 1

... I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION Part NO. M52D16161A-10TG 100MHz 50 PIN TSOP(II) M52D16161A-10BG 100MHz ...

Page 2

... CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS , WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. M52D16161A LWE LDQM DQi LDQM LWCBR L(U)DQM Input Function Publication Date : Apr ...

Page 3

... OL ≤ 3ns acceptable. ≤ 3ns acceptable all other pins are not under test = 0V. DDQ ≤ OUT DDQ = 1MHz) ° Symbol C CLK ADD C OUT M52D16161A Value -1.0 ~ 4.6 -1.0 ~ 4.6 - 150 0.7 50 ° C ° Typ Max Unit 1.8 1.9 V 1.8 V +0.3 V DDQ 0 0 ...

Page 4

... V (min), CLK V (max Input signals are stable I = 0Ma, Page Burst OL All Band Activated, tCCD = tCCD (min) ≥ (min TCSR range ≤ CKE 0.2V ≤ CKE 0.2V M52D16161A ° CAS Version Latency -10 - 0.12 ∞ = 0.1 =15ns 5.5 ∞ 1.5 ∞ =15ns 10 ∞ ...

Page 5

... RP t (min) 50 RAS t (max) RAS t (min (min) CDL t (min) RDL t (min) BDL t (min) CCD CAS latency=3 CAS latency=2 M52D16161A Unit / 0 DDQ ns V DDQ Vtt =0.5x VDDQ 50 Z0= (Fig.2) AC Output Load Circuit Version Unit - 100 us 90 ...

Page 6

... SAC - SLZ - 7 t SHZ - 8 *All AC parameters are measured from half to half. M52D16161A -15 Unit Note Min Max 15 1000 2 ...

Page 7

... A0-A11 Elite Semiconductor Memory Technology Inc LTMODE WT BL LTMODE RAS WE M52D16161A Address bus Burst Read and Single Write (for Write Through Cache) Mode Register Set A2-A0 000 001 010 Burst length 011 100 101 110 111 0 Wrap type ...

Page 8

... A10 Elite Semiconductor Memory Technology Inc PASR DS M52D16161A Address bus Extended Mode Register Set A2-A0 WT=0 000 2 Banks 001 1 Bank (Bank 0, BA=0) 010 1/2 Bank (BA=A10=0) PASR 011 100 101 1/4 Bank (BA=A10=A9=0) 110 111 A6-A5 Driver Strength 00 Full Strength ...

Page 9

... M52D16161A Interleave Addressing Sequence (decimal Interleave Addressing Sequence (decimal ...

Page 10

... Entry Exit Entry Exit (V= Valid, X= Don’t Care, H= Logic High , L = Logic Low) after the end of burst. RP M52D16161A DQM BA A10/AP A9~A0 Note RAS CAS ...

Page 11

... M52D16161A *Note2,3 *Note4 *Note2 *Note 3 *Note4 ...

Page 12

... Enable auto precharge, precharge bank A at end of burst. 1 Enable auto precharge, precharge bank B at end of burst. 4.A10/AP and BA control bank precharge when precharge command is asserted. A10/AP BA precharge 0 0 Bank Bank Both Banks Elite Semiconductor Memory Technology Inc. Operation M52D16161A Publication Date : Apr. 2007 Revision : 1.5 12/29 ...

Page 13

... Elite Semiconductor Memory Technology Inc M52D16161A ...

Page 14

... Qa1 Qa3 Qa1 Qa3 Qa0 Qa2 Precharge Row Active (A- Bank) (A- Bank) ) after the clock. SHZ +CAS latency-1)+t RCD M52D16161A Cb0 Rb Db0 Db1 Db2 Db3 *Note4 Db0 Db2 Db1 Db3 *Note4 ...

Page 15

... HIGH Cb0 Qa0 Qb0 Qb1 Qa1 Qb2 Qa1 Qb0 Qb1 Qa0 *Note1 Read (A-Bank) before Row precharge, will be written. RDL M52D16161A *Note2 Cc0 Cd0 t RDL Dc0 Dc1 Dd1 Dd0 Dc0 Dc1 Dd0 Dd2 t CDL *Note3 ...

Page 16

... HIGH RBb CBb RBb QAa0 QAa1 QAa2 QAa3 QBb1 QBb2 QBb0 QAa0 QAa1 QAa2 QAa3 QBb0 Read (B-Bank) Row Active (B-Bank) M52D16161A CAc CBd CAe QBb3 QAc0 QAc1 QBd0 QBd1 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 Read ...

Page 17

... Elite Semiconductor Memory Technology Inc HIGH RBb CBb RBb DBb2 DBb3 DAa1 DAa2 DAa3 DBb0 DBb1 t CDL Write (B-Bank) M52D16161A *Note2 CAc CBd DAc0 DAc1 DBd0 DBd1 t RDL *Note1 Precharge Write (Both Banks) (A-Bank) Write (B-Bank) Publication Date : Apr ...

Page 18

... ESMT Read & Write Cycle at Different Bank @ Burst Length = 4 *Note: 1.t should be met to complete write. CDL Elite Semiconductor Memory Technology Inc. M52D16161A Publication Date : Apr. 2007 Revision : 1.5 18/29 ...

Page 19

... Read with Auto Precharge Start Point ( A - Bank ) ( A - Bank) before internal precharge start RAS M52D16161A ...

Page 20

... Elite Semiconductor Memory Technology Inc M52D16161A ...

Page 21

... *Note2 M52D16161A ...

Page 22

... M52D16161A Publication Date : Apr ...

Page 23

... Row Active ( (B-Bank) Read with Auto Precharge (A-Bank) M52D16161A * ...

Page 24

... Row Active Precharge Active Active Power-Down Power-down Power-down Exit Exit Entry M52D16161A Read Publication Date : Apr. 2007 Revision : 1 ...

Page 25

... *Note3 required before exit from self refresh. RAS M52D16161A Publication Date : Apr ...

Page 26

... CS , RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register. 2.Minimum 2 clock cycles should be met before new RAS activation. 3.Please refer to Mode Register Set table. Elite Semiconductor Memory Technology Inc. Auto Refresh Cycle M52D16161A ...

Page 27

... Elite Semiconductor Memory Technology Inc. Nom Max - 1.20 0.127 0.203 1.00 1.05 - 0.45 0.35 0.40 - 0.21 0.127 0.16 20.95 21.08 11.76 11.96 10.16 10.29 0.50 0.60 0.80 REF 0.80 BSC - 8 M52D16161A Dimension in inch Min Nom - - 0.002 0.005 0.037 0.039 0.012 - 0.012 0.014 0.005 - 0.004 0.005 0.820 0.825 0.455 0.463 0.394 0.400 0.016 0.020 0.031 REF 0.031 BSC 0 - Publication Date : Apr. 2007 Revision : 1 ...

Page 28

... Controlling dimension : Millimeter. Elite Semiconductor Memory Technology Inc. Dimension in mm Min Norm Max Min 1.00 0.20 0.25 0.30 0.008 0.61 0.66 0.71 0.024 0.30 0.35 0.40 0.012 6.30 6.40 6.50 0.248 10.00 10.10 10.20 0.394 3.90 9.10 0.65 M52D16161A Dimension in inch Norm Max 0.039 0.010 0.012 0.026 0.028 0.014 0.016 0.252 0.256 0.398 0.402 0.154 0.358 0.026 Publication Date : Apr. 2007 Revision : 1.5 28/29 ...

Page 29

... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Important Notice M52D16161A Publication Date : Apr. 2007 Revision : 1.5 29/29 ...