M52D16161A-10BG ESMT [Elite Semiconductor Memory Technology Inc.], M52D16161A-10BG Datasheet - Page 15

• Manufacturer Part Number: M52D16161A-10BG
• Description: 512K x 16Bit x 2Banks Synchronous DRAM
• Manufacturer: ESMT [Elite Semiconductor Memory Technology Inc.]

ESMT
Page Read & Write Cycle at Same Bank @ Burst Length=4
*Note :1.To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus
Elite Semiconductor Memory Technology Inc.
DQ
CLOCK
A10/AP
CL=3
CL=2
ADDR
DQM
CKE
RAS
CAS
WE
CS
BA
2.Row precharge will interrupt writing. Last data input, t
3.DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
contention.
Input data after Row precharge cycle will be masked internally.
0
Row Active
(A-Bank)
Ra
Ra
1
2
t
RCD
3
(A-Bank)
Read
Ca0
4
5
(A-Bank)
Cb0
Read
Qa0
6
Qa1
Qa0
7
Qb0
Qa1
8
*Note1
Qb1
Qb0
RDL
9
before Row precharge, will be written.
Qb1
Qb2
HIGH
10
11
(A-Bank)
Write
Cc0
Dc0
Dc0
12
t
CDL
Dc1
Dc1
13
(A-Bank)
Write
Cd0
Dd0
Dd0
Revision : 1.5
Publication Date : Apr. 2007
14
M52D16161A
Dd2
Dd1
15
t
RDL
16
Precharge
(A-Bank)
*Note3
*Note2
17
18
15/29
: Don't care
19