HN58S256AT-20 HITACHI [Hitachi Semiconductor], HN58S256AT-20 Datasheet - Page 6

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HN58S256AT-20

Manufacturer Part Number
HN58S256AT-20
Description
256 k EEPROM (32-kword x 8-bit)
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
HN58S256A Series
Write Cycle
Parameter
Address setup time
Address hold time
CE to write setup time (WE controlled)
CE hold time (WE controlled)
WE to write setup time (CE controlled)
WE hold time (CE controlled)
OE to write setup time
OE hold time
Data setup time
Data hold time
WE pulse width (WE controlled)
CE pulse width (CE controlled)
Data latch time
Byte load cycle
Byte load window
Write cycle time
Write start time
Notes: 1. t
2. Use this device in longer cycle than this value.
3. t
4. Next read or write operation can be initiated after t
5. A6 through A14 are page addresses and these addresses are latched at the first falling edge
6. A6 through A14 are page addresses and these addresses are latched at the first falling edge
7. See AC characteristics.
longer driven.
completes the internal write operation within this value.
of WE.
of CE.
DF
WC
is defined as the time at which the outputs achieve the open circuit conditions and are no
must be longer than this value unless polling techniques is used. This device automatically
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AS
AH
CS
CH
WS
WH
OES
OEH
DS
DH
WP
CW
DL
BLC
BL
WC
DW
Min*
0
150
0
0
0
0
0
0
150
0
200
200
200
0.4
100
0*
DW
4
if polling techniques is used.
2
Typ
Max
30
15*
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
s
s
Test conditions

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