ADV601JS Analog Devices, ADV601JS Datasheet - Page 21

• Manufacturer Part Number: ADV601JS
• Description: Low Cost Multiformat Video Codec
• Manufacturer: Analog Devices

Video Interface
The ADV601 video interface supports a wide range of compo-
nent digital video (D1) interfaces in both compression (input)
and decompression (output) modes. These digital video inter-
faces include support for the following:
• Philips 4:2:2
• Multiplexed Philips 4:2:2
• CCIR-656/SMPTE125M - international standard
• Closed Captioning and VITC decode and encode
Video interface master and slave modes allow for the generation
or receiving of synchronization and blanking signals. Definitions
for the different formats can be found later in this section. For
recommended connections to popular video decoders and
encoders, see the Connecting The ADV601 To Popular Video
Decoders and Encoders section. A complete list of supported
video interfaces and sampling rates is included in Table V.
Name
CCIR-656
Multiplex
Philips
Gray Scale 8, 10, or 12
Internally, the video interface translates all video formats to one
consistent format to be passed to the wavelet kernel. This con-
sistent internal video standard is 4:2:2 at 16 bits accuracy.
VITC and Closed Captioning Support
The video interface also supports the direct loss-less extraction
of 90-bit VITC codes during encode and the insertion of VITC
codes during decode. Closed Captioning data (found on active
Video Line 21) is handled just as normal active video on an
active scan line. As a result, no special dedicated support is
necessary for Closed Captioning. The data rates for Closed
Captioning data are low enough to ensure robust operation of
this mechanism at compression ratios of 50:1 and higher. Note
that you must include Video Line 21 in the ADV601’s defined
active video area for Closed Caption support.
27 MHz Nominal Sampling
There is one clock input (VCLK) to support all internal process-
ing elements. This is a 50% duty cycle signal and must be syn-
chronous to the video data. Internally this clock is doubled using
a phase locked loop to provide for a 54 MHz internal processing
clock. The clock interface is a two pin interface that allows a
crystal oscillator to be tied across the pins or a clock oscillator to
drive one pin. The nominal clock rate for the video interface is
27 MHz. Note that the ADV601 also supports pixel rates ranging
from 12.27 MHz to 14.75 MHz (VCLK rates from 24.54 MHz to
29.5 MHz).
Video Interface and Modes
In all, there are seven programmable features that configure the
video interface. These are:
REV. 0
Philips
Table V. Component Digital Video Interfaces
Bits/
Component Space
8 or 10
8 or 10
8 or 10
Color
YCrCb 4:2:2
YUV
YUV
Luma
Sampling Rate (MHz) I/F Width
4:2:2
4:2:2
4:0:0
<= 29.5
12.27-14.79
Nominal
Date
27
12.27-14.79
8 or 10
8 or 10
16 or 20
8, 10 or 12
–21–
• Encode-Decode Control
• Master-Slave Control
• 525-625 (NTSC-PAL) Control
Square
Pixel
Control
0
0
1
1
• Square Pixel Control
• Bipolar/Unipolar Color Component
In addition to determining what functions the internal pro-
cessing elements must perform, this control determines the
direction of the video interface. In decode mode, the video
interface outputs data. In encode mode, the interface receives
data. The state of the control is reflected on the ENC pin.
This pin can be used as an enable input by external line driv-
ers. This control is maintained by the host processor.
This control determines whether the ADV601 generates or
receives the VSYNC, HSYNC, CREF, and FIELD signals. In
master mode, the ADV601 generates these signals for external
hardware synchronization. In slave mode, the ADV601 re-
ceives these signals. Note that some video formats require the
ADV601 to operate in slave mode only. This control is main-
tained by the host processor.
This control determines whether the ADV601 is operating on
525/NTSC video or 625/PAL video. This information is used
when the ADV601 is in master and decode modes so that the
ADV601 knows where and when to generate the HSYNC,
VSYNC, and FIELD Pulses as well as when to insert the SAV
and EAV time codes (for CCIR-656 only) in the data stream.
This control is maintained by the host processor. Table VI
shows how the 525-625 Control and Square Pixel Control in
the Mode Control register work together.
This control determines whether the ADV601 is operating on
square pixel video. For square pixel NTSC, the 525-625
Control is set to 525 and the Square Pixel Control is asserted.
For square pixel PAL, the 525-625 Control is set to 625 and
the Square Pixel Control is asserted. Also note that the VCLK
input differs for NTSC and PAL video.
This mode determines whether offsets are used on color com-
ponents. In Philips mode, this control is usually set to Bipo-
lar, since the color components are normal twos-compliment
signed values. In CCIR-656 mode, this control is set to Uni-
polar, since the color components are offset by 128. Note that
it is likely the ADV601 will function if this control is in the
wrong state, but compression performance will be degraded.
It is important to set this bit correctly.
Table VI. Square Pixel Control, 525-625 Control, and
Video Formats
525-625
Control
0
1
0
1
Max
Horizontal
Size
720
720
640
768
Max
Field
Size
243
288
243
288
NTSC-PAL
CCIR-601 NTSC
CCIR-601 PAL
Square Pixel NTSC
Square Pixel PAL
ADV601